131 lines
4.2 KiB
ArmAsm
131 lines
4.2 KiB
ArmAsm
// +build arm64,go1.16
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// Taken from https://github.com/bwesterb/armed-keccak
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#include "textflag.h"
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// func f1600x2ARM(state *uint64, rc *[24]uint64)
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TEXT ·f1600x2ARM(SB), NOSPLIT, $0-16
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MOVD state+0(FP), R0
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MOVD rc+8(FP), R1
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MOVD R0, R2
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MOVD $24, R3
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VLD1.P 64(R0), [ V0.B16, V1.B16, V2.B16, V3.B16]
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VLD1.P 64(R0), [ V4.B16, V5.B16, V6.B16, V7.B16]
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VLD1.P 64(R0), [ V8.B16, V9.B16, V10.B16, V11.B16]
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VLD1.P 64(R0), [V12.B16, V13.B16, V14.B16, V15.B16]
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VLD1.P 64(R0), [V16.B16, V17.B16, V18.B16, V19.B16]
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VLD1.P 64(R0), [V20.B16, V21.B16, V22.B16, V23.B16]
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VLD1.P (R0), [V24.B16]
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loop:
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// Execute theta but without xorring into the state yet.
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VEOR3 V10.B16, V5.B16, V0.B16, V25.B16
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VEOR3 V11.B16, V6.B16, V1.B16, V26.B16
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VEOR3 V12.B16, V7.B16, V2.B16, V27.B16
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VEOR3 V13.B16, V8.B16, V3.B16, V28.B16
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VEOR3 V14.B16, V9.B16, V4.B16, V29.B16
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VEOR3 V20.B16, V15.B16, V25.B16, V25.B16
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VEOR3 V21.B16, V16.B16, V26.B16, V26.B16
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VEOR3 V22.B16, V17.B16, V27.B16, V27.B16
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VEOR3 V23.B16, V18.B16, V28.B16, V28.B16
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VEOR3 V24.B16, V19.B16, V29.B16, V29.B16
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// Xor parities from step theta into the state at the same time as
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// exeuting rho and pi.
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VRAX1 V26.D2, V29.D2, V30.D2
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VRAX1 V29.D2, V27.D2, V29.D2
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VRAX1 V27.D2, V25.D2, V27.D2
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VRAX1 V25.D2, V28.D2, V25.D2
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VRAX1 V28.D2, V26.D2, V28.D2
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VEOR V30.B16, V0.B16, V0.B16
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VMOV V1.B16, V31.B16
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VXAR $20, V27.D2, V6.D2, V1.D2
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VXAR $44, V25.D2, V9.D2, V6.D2
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VXAR $3 , V28.D2, V22.D2, V9.D2
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VXAR $25, V25.D2, V14.D2, V22.D2
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VXAR $46, V30.D2, V20.D2, V14.D2
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VXAR $2 , V28.D2, V2.D2, V20.D2
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VXAR $21, V28.D2, V12.D2, V2.D2
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VXAR $39, V29.D2, V13.D2, V12.D2
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VXAR $56, V25.D2, V19.D2, V13.D2
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VXAR $8 , V29.D2, V23.D2, V19.D2
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VXAR $23, V30.D2, V15.D2, V23.D2
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VXAR $37, V25.D2, V4.D2, V15.D2
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VXAR $50, V25.D2, V24.D2, V4.D2
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VXAR $62, V27.D2, V21.D2, V24.D2
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VXAR $9 , V29.D2, V8.D2, V21.D2
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VXAR $19, V27.D2, V16.D2, V8.D2
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VXAR $28, V30.D2, V5.D2, V16.D2
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VXAR $36, V29.D2, V3.D2, V5.D2
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VXAR $43, V29.D2, V18.D2, V3.D2
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VXAR $49, V28.D2, V17.D2, V18.D2
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VXAR $54, V27.D2, V11.D2, V17.D2
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VXAR $58, V28.D2, V7.D2, V11.D2
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VXAR $61, V30.D2, V10.D2, V7.D2
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VXAR $63, V27.D2, V31.D2, V10.D2
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// Chi
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VBCAX V1.B16, V2.B16, V0.B16, V25.B16
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VBCAX V2.B16, V3.B16, V1.B16, V26.B16
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VBCAX V3.B16, V4.B16, V2.B16, V2.B16
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VBCAX V4.B16, V0.B16, V3.B16, V3.B16
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VBCAX V0.B16, V1.B16, V4.B16, V4.B16
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VMOV V25.B16, V0.B16
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VMOV V26.B16, V1.B16
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VBCAX V6.B16, V7.B16, V5.B16, V25.B16
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VBCAX V7.B16, V8.B16, V6.B16, V26.B16
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VBCAX V8.B16, V9.B16, V7.B16, V7.B16
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VBCAX V9.B16, V5.B16, V8.B16, V8.B16
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VBCAX V5.B16, V6.B16, V9.B16, V9.B16
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VMOV V25.B16, V5.B16
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VMOV V26.B16, V6.B16
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VBCAX V11.B16, V12.B16, V10.B16, V25.B16
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VBCAX V12.B16, V13.B16, V11.B16, V26.B16
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VBCAX V13.B16, V14.B16, V12.B16, V12.B16
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VBCAX V14.B16, V10.B16, V13.B16, V13.B16
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VBCAX V10.B16, V11.B16, V14.B16, V14.B16
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VMOV V25.B16, V10.B16
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VMOV V26.B16, V11.B16
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VBCAX V16.B16, V17.B16, V15.B16, V25.B16
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VBCAX V17.B16, V18.B16, V16.B16, V26.B16
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VBCAX V18.B16, V19.B16, V17.B16, V17.B16
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VBCAX V19.B16, V15.B16, V18.B16, V18.B16
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VBCAX V15.B16, V16.B16, V19.B16, V19.B16
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VMOV V25.B16, V15.B16
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VMOV V26.B16, V16.B16
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VBCAX V21.B16, V22.B16, V20.B16, V25.B16
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VBCAX V22.B16, V23.B16, V21.B16, V26.B16
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VBCAX V23.B16, V24.B16, V22.B16, V22.B16
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VBCAX V24.B16, V20.B16, V23.B16, V23.B16
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VBCAX V20.B16, V21.B16, V24.B16, V24.B16
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VMOV V25.B16, V20.B16
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VMOV V26.B16, V21.B16
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// Iota
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VLD1R.P 8(R1), [V25.D2]
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VEOR V25.B16, V0.B16, V0.B16
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SUBS $1, R3, R3
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CBNZ R3, loop
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MOVD R2, R0
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VST1.P [ V0.B16, V1.B16, V2.B16, V3.B16], 64(R0)
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VST1.P [ V4.B16, V5.B16, V6.B16, V7.B16], 64(R0)
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VST1.P [ V8.B16, V9.B16, V10.B16, V11.B16], 64(R0)
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VST1.P [V12.B16, V13.B16, V14.B16, V15.B16], 64(R0)
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VST1.P [V16.B16, V17.B16, V18.B16, V19.B16], 64(R0)
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VST1.P [V20.B16, V21.B16, V22.B16, V23.B16], 64(R0)
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VST1.P [V24.B16], (R0)
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RET
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