2018-10-17 06:33:19 +00:00
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#define _POSIX_C_SOURCE 200112L
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2017-05-01 03:20:48 +00:00
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#include <assert.h>
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2019-01-29 11:04:12 +00:00
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#include <drm_fourcc.h>
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2017-05-01 03:20:48 +00:00
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#include <drm_mode.h>
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#include <EGL/egl.h>
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#include <EGL/eglext.h>
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2018-02-12 20:29:23 +00:00
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#include <errno.h>
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2017-05-01 03:20:48 +00:00
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#include <gbm.h>
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2017-08-07 09:07:42 +00:00
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#include <GLES2/gl2.h>
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#include <GLES2/gl2ext.h>
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2018-02-12 20:29:23 +00:00
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <time.h>
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2017-05-02 02:08:34 +00:00
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#include <wayland-server.h>
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2018-02-06 21:45:37 +00:00
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#include <wayland-util.h>
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2017-06-04 23:30:37 +00:00
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#include <wlr/backend/interface.h>
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2017-06-21 14:27:45 +00:00
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#include <wlr/interfaces/wlr_output.h>
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2018-02-12 20:29:23 +00:00
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#include <wlr/render/gles2.h>
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2018-03-19 22:16:29 +00:00
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#include <wlr/render/wlr_renderer.h>
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2018-03-15 08:11:03 +00:00
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#include <wlr/types/wlr_matrix.h>
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2018-02-12 20:29:23 +00:00
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#include <wlr/util/log.h>
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#include <xf86drm.h>
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#include <xf86drmMode.h>
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2017-09-30 06:03:34 +00:00
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#include "backend/drm/drm.h"
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2017-09-30 06:11:41 +00:00
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#include "backend/drm/iface.h"
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2017-09-30 06:03:34 +00:00
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#include "backend/drm/util.h"
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2018-02-12 20:29:23 +00:00
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#include "util/signal.h"
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2017-05-01 03:20:48 +00:00
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2018-04-25 22:24:58 +00:00
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bool check_drm_features(struct wlr_drm_backend *drm) {
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2018-10-01 20:44:33 +00:00
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uint64_t cap;
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2018-08-05 06:25:25 +00:00
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if (drm->parent) {
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if (drmGetCap(drm->fd, DRM_CAP_PRIME, &cap) ||
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!(cap & DRM_PRIME_CAP_IMPORT)) {
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wlr_log(WLR_ERROR,
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"PRIME import not supported on secondary GPU");
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return false;
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}
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if (drmGetCap(drm->parent->fd, DRM_CAP_PRIME, &cap) ||
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!(cap & DRM_PRIME_CAP_EXPORT)) {
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wlr_log(WLR_ERROR,
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"PRIME export not supported on primary GPU");
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return false;
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}
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}
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2017-09-30 09:22:26 +00:00
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if (drmSetClientCap(drm->fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES, 1)) {
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2018-07-09 21:49:54 +00:00
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wlr_log(WLR_ERROR, "DRM universal planes unsupported");
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2017-08-05 06:15:39 +00:00
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return false;
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}
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2018-05-03 12:05:47 +00:00
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const char *no_atomic = getenv("WLR_DRM_NO_ATOMIC");
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if (no_atomic && strcmp(no_atomic, "1") == 0) {
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2018-10-01 20:44:33 +00:00
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wlr_log(WLR_DEBUG,
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"WLR_DRM_NO_ATOMIC set, forcing legacy DRM interface");
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2017-10-02 08:44:33 +00:00
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drm->iface = &legacy_iface;
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2017-09-30 09:22:26 +00:00
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} else if (drmSetClientCap(drm->fd, DRM_CLIENT_CAP_ATOMIC, 1)) {
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2018-10-01 20:44:33 +00:00
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wlr_log(WLR_DEBUG,
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"Atomic modesetting unsupported, using legacy DRM interface");
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2017-10-02 08:44:33 +00:00
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drm->iface = &legacy_iface;
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2017-08-09 08:43:01 +00:00
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} else {
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2018-07-09 21:49:54 +00:00
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wlr_log(WLR_DEBUG, "Using atomic DRM interface");
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2017-10-02 08:44:33 +00:00
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drm->iface = &atomic_iface;
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2017-08-05 06:15:39 +00:00
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}
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2018-10-01 20:44:33 +00:00
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int ret = drmGetCap(drm->fd, DRM_CAP_TIMESTAMP_MONOTONIC, &cap);
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drm->clock = (ret == 0 && cap == 1) ? CLOCK_MONOTONIC : CLOCK_REALTIME;
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2017-08-05 06:15:39 +00:00
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return true;
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}
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2017-08-09 08:43:01 +00:00
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static int cmp_plane(const void *arg1, const void *arg2) {
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2017-07-20 08:51:59 +00:00
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const struct wlr_drm_plane *a = arg1;
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const struct wlr_drm_plane *b = arg2;
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return (int)a->type - (int)b->type;
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}
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2017-09-30 09:22:26 +00:00
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static bool init_planes(struct wlr_drm_backend *drm) {
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drmModePlaneRes *plane_res = drmModeGetPlaneResources(drm->fd);
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2017-07-20 08:51:59 +00:00
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if (!plane_res) {
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2018-07-09 21:49:54 +00:00
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wlr_log_errno(WLR_ERROR, "Failed to get DRM plane resources");
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2017-07-20 08:51:59 +00:00
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return false;
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}
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2018-07-09 21:49:54 +00:00
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wlr_log(WLR_INFO, "Found %"PRIu32" DRM planes", plane_res->count_planes);
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2017-07-20 08:51:59 +00:00
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if (plane_res->count_planes == 0) {
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drmModeFreePlaneResources(plane_res);
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return true;
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}
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2017-09-30 09:22:26 +00:00
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drm->num_planes = plane_res->count_planes;
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drm->planes = calloc(drm->num_planes, sizeof(*drm->planes));
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if (!drm->planes) {
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2018-07-09 21:49:54 +00:00
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wlr_log_errno(WLR_ERROR, "Allocation failed");
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2017-07-20 08:51:59 +00:00
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goto error_res;
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}
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2017-09-30 09:22:26 +00:00
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for (size_t i = 0; i < drm->num_planes; ++i) {
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struct wlr_drm_plane *p = &drm->planes[i];
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2017-07-20 08:51:59 +00:00
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2017-09-30 09:22:26 +00:00
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drmModePlane *plane = drmModeGetPlane(drm->fd, plane_res->planes[i]);
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2017-07-20 08:51:59 +00:00
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if (!plane) {
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2018-07-09 21:49:54 +00:00
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wlr_log_errno(WLR_ERROR, "Failed to get DRM plane");
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2017-07-20 08:51:59 +00:00
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goto error_planes;
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}
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p->id = plane->plane_id;
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p->possible_crtcs = plane->possible_crtcs;
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2019-01-29 11:04:12 +00:00
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uint64_t type;
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2018-04-25 22:24:58 +00:00
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if (!get_drm_plane_props(drm->fd, p->id, &p->props) ||
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!get_drm_prop(drm->fd, p->id, p->props.type, &type)) {
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2017-07-20 08:51:59 +00:00
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drmModeFreePlane(plane);
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goto error_planes;
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}
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p->type = type;
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2017-09-30 09:22:26 +00:00
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drm->num_type_planes[type]++;
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2017-07-20 08:51:59 +00:00
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2019-01-29 11:04:12 +00:00
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// Choose an RGB format for the plane
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uint32_t rgb_format = DRM_FORMAT_INVALID;
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for (size_t j = 0; j < plane->count_formats; ++j) {
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uint32_t fmt = plane->formats[j];
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if (fmt == DRM_FORMAT_ARGB8888) {
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// Prefer formats with alpha channel
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rgb_format = fmt;
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break;
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} else if (fmt == DRM_FORMAT_XRGB8888) {
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rgb_format = fmt;
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}
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}
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if (rgb_format == DRM_FORMAT_INVALID) {
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wlr_log(WLR_ERROR, "Failed to find an RGB format for plane %zu", i);
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drmModeFreePlane(plane);
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goto error_planes;
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}
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p->drm_format = rgb_format;
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2017-07-20 08:51:59 +00:00
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drmModeFreePlane(plane);
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}
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2018-07-09 21:49:54 +00:00
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wlr_log(WLR_INFO, "(%zu overlay, %zu primary, %zu cursor)",
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2017-09-30 09:22:26 +00:00
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drm->num_overlay_planes,
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drm->num_primary_planes,
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drm->num_cursor_planes);
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2017-07-20 08:51:59 +00:00
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2017-09-30 09:22:26 +00:00
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qsort(drm->planes, drm->num_planes, sizeof(*drm->planes), cmp_plane);
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2017-07-20 08:51:59 +00:00
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2017-09-30 09:22:26 +00:00
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drm->overlay_planes = drm->planes;
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drm->primary_planes = drm->overlay_planes
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+ drm->num_overlay_planes;
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drm->cursor_planes = drm->primary_planes
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+ drm->num_primary_planes;
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2017-07-20 08:51:59 +00:00
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2017-08-11 22:02:04 +00:00
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drmModeFreePlaneResources(plane_res);
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2017-07-20 08:51:59 +00:00
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return true;
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error_planes:
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2017-09-30 09:22:26 +00:00
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free(drm->planes);
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2017-07-20 08:51:59 +00:00
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error_res:
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drmModeFreePlaneResources(plane_res);
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return false;
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}
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2018-04-25 22:24:58 +00:00
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bool init_drm_resources(struct wlr_drm_backend *drm) {
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2017-09-30 09:22:26 +00:00
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drmModeRes *res = drmModeGetResources(drm->fd);
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2017-07-20 08:51:59 +00:00
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if (!res) {
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2018-07-09 21:49:54 +00:00
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wlr_log_errno(WLR_ERROR, "Failed to get DRM resources");
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2017-07-20 08:51:59 +00:00
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return false;
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}
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2018-07-09 21:49:54 +00:00
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wlr_log(WLR_INFO, "Found %d DRM CRTCs", res->count_crtcs);
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2017-07-20 08:51:59 +00:00
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2017-09-30 09:22:26 +00:00
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drm->num_crtcs = res->count_crtcs;
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2018-10-07 10:59:00 +00:00
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if (drm->num_crtcs == 0) {
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drmModeFreeResources(res);
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return true;
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}
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2017-09-30 09:22:26 +00:00
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drm->crtcs = calloc(drm->num_crtcs, sizeof(drm->crtcs[0]));
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if (!drm->crtcs) {
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2018-07-09 21:49:54 +00:00
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wlr_log_errno(WLR_ERROR, "Allocation failed");
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2017-07-20 08:51:59 +00:00
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goto error_res;
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}
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2017-09-30 09:22:26 +00:00
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for (size_t i = 0; i < drm->num_crtcs; ++i) {
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struct wlr_drm_crtc *crtc = &drm->crtcs[i];
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2017-07-20 08:51:59 +00:00
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crtc->id = res->crtcs[i];
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2018-02-04 20:03:44 +00:00
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crtc->legacy_crtc = drmModeGetCrtc(drm->fd, crtc->id);
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2018-04-25 22:24:58 +00:00
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get_drm_crtc_props(drm->fd, crtc->id, &crtc->props);
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2017-07-20 08:51:59 +00:00
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}
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2017-09-30 09:22:26 +00:00
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if (!init_planes(drm)) {
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2017-07-20 08:51:59 +00:00
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goto error_crtcs;
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}
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drmModeFreeResources(res);
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return true;
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error_crtcs:
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2017-09-30 09:22:26 +00:00
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free(drm->crtcs);
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2017-07-20 08:51:59 +00:00
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error_res:
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drmModeFreeResources(res);
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return false;
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}
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2018-04-25 22:24:58 +00:00
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void finish_drm_resources(struct wlr_drm_backend *drm) {
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2017-09-30 09:22:26 +00:00
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if (!drm) {
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2017-08-05 07:49:34 +00:00
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return;
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2017-08-06 22:15:05 +00:00
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}
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2017-09-30 09:22:26 +00:00
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for (size_t i = 0; i < drm->num_crtcs; ++i) {
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struct wlr_drm_crtc *crtc = &drm->crtcs[i];
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2017-08-09 08:43:01 +00:00
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drmModeAtomicFree(crtc->atomic);
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2018-02-04 20:03:44 +00:00
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drmModeFreeCrtc(crtc->legacy_crtc);
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2017-08-09 08:43:01 +00:00
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if (crtc->mode_id) {
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2017-09-30 09:22:26 +00:00
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drmModeDestroyPropertyBlob(drm->fd, crtc->mode_id);
|
2017-08-09 08:43:01 +00:00
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}
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2018-02-01 19:27:35 +00:00
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if (crtc->gamma_lut) {
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drmModeDestroyPropertyBlob(drm->fd, crtc->gamma_lut);
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}
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2018-10-03 08:53:35 +00:00
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free(crtc->gamma_table);
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2017-08-09 08:43:01 +00:00
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}
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2017-10-05 20:01:56 +00:00
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2017-09-30 09:22:26 +00:00
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free(drm->crtcs);
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free(drm->planes);
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2017-08-05 07:49:34 +00:00
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}
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2018-09-17 20:25:20 +00:00
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static struct wlr_drm_connector *get_drm_connector_from_output(
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struct wlr_output *wlr_output) {
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assert(wlr_output_is_drm(wlr_output));
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return (struct wlr_drm_connector *)wlr_output;
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}
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2018-04-21 10:42:18 +00:00
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static bool drm_connector_make_current(struct wlr_output *output,
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2018-01-20 23:06:35 +00:00
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int *buffer_age) {
|
2018-09-17 20:25:20 +00:00
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struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
2018-04-25 22:24:58 +00:00
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return make_drm_surface_current(&conn->crtc->primary->surf, buffer_age);
|
2017-05-03 10:40:19 +00:00
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}
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2018-04-21 10:42:18 +00:00
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static bool drm_connector_swap_buffers(struct wlr_output *output,
|
2018-02-09 21:54:14 +00:00
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pixman_region32_t *damage) {
|
2018-09-17 20:25:20 +00:00
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struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
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struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-01-27 10:16:42 +00:00
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if (!drm->session->active) {
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return false;
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}
|
2017-09-30 09:22:26 +00:00
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2017-09-30 10:31:08 +00:00
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struct wlr_drm_crtc *crtc = conn->crtc;
|
2018-01-21 20:37:23 +00:00
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if (!crtc) {
|
2018-01-21 21:16:55 +00:00
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return false;
|
2018-01-21 20:37:23 +00:00
|
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}
|
2017-08-05 05:27:59 +00:00
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struct wlr_drm_plane *plane = crtc->primary;
|
2017-05-03 10:40:19 +00:00
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|
2018-04-25 22:24:58 +00:00
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struct gbm_bo *bo = swap_drm_surface_buffers(&plane->surf, damage);
|
2017-10-01 06:22:47 +00:00
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if (drm->parent) {
|
2018-04-25 22:24:58 +00:00
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bo = copy_drm_surface_mgpu(&plane->mgpu_surf, bo);
|
2017-10-01 06:22:47 +00:00
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}
|
2019-01-29 11:04:12 +00:00
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|
uint32_t fb_id = get_fb_for_bo(bo, plane->drm_format);
|
2017-09-23 06:27:14 +00:00
|
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|
|
2018-01-19 22:46:40 +00:00
|
|
|
if (conn->pageflip_pending) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_ERROR, "Skipping pageflip on output '%s'", conn->output.name);
|
2018-01-28 21:39:24 +00:00
|
|
|
return false;
|
2018-01-19 22:46:40 +00:00
|
|
|
}
|
|
|
|
|
2018-01-28 22:33:38 +00:00
|
|
|
if (!drm->iface->crtc_pageflip(drm, conn, crtc, fb_id, NULL)) {
|
|
|
|
return false;
|
2017-09-23 06:27:14 +00:00
|
|
|
}
|
2018-01-20 23:06:35 +00:00
|
|
|
|
2018-01-28 22:33:38 +00:00
|
|
|
conn->pageflip_pending = true;
|
2018-02-02 23:15:44 +00:00
|
|
|
wlr_output_update_enabled(output, true);
|
2018-01-20 23:06:35 +00:00
|
|
|
return true;
|
2017-06-21 01:31:29 +00:00
|
|
|
}
|
|
|
|
|
2018-10-03 08:36:33 +00:00
|
|
|
static void fill_empty_gamma_table(size_t size,
|
2018-07-22 16:37:01 +00:00
|
|
|
uint16_t *r, uint16_t *g, uint16_t *b) {
|
|
|
|
for (uint32_t i = 0; i < size; ++i) {
|
2018-07-22 21:57:22 +00:00
|
|
|
uint16_t val = (uint32_t)0xffff * i / (size - 1);
|
2018-07-22 16:37:01 +00:00
|
|
|
r[i] = g[i] = b[i] = val;
|
2018-02-04 20:50:52 +00:00
|
|
|
}
|
2017-09-06 16:53:08 +00:00
|
|
|
}
|
|
|
|
|
2018-10-03 08:36:33 +00:00
|
|
|
static size_t drm_connector_get_gamma_size(struct wlr_output *output) {
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-02-04 20:50:52 +00:00
|
|
|
|
|
|
|
if (conn->crtc) {
|
|
|
|
return drm->iface->crtc_get_gamma_size(drm, conn->crtc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2017-09-06 16:53:08 +00:00
|
|
|
}
|
|
|
|
|
2018-10-03 08:53:35 +00:00
|
|
|
bool set_drm_connector_gamma(struct wlr_output *output, size_t size,
|
2018-10-03 08:36:33 +00:00
|
|
|
const uint16_t *r, const uint16_t *g, const uint16_t *b) {
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-07-22 16:37:01 +00:00
|
|
|
|
|
|
|
if (!conn->crtc) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-10-03 08:36:33 +00:00
|
|
|
bool reset = false;
|
2018-07-22 16:37:01 +00:00
|
|
|
if (size == 0) {
|
2018-10-03 08:36:33 +00:00
|
|
|
reset = true;
|
2018-07-22 16:37:01 +00:00
|
|
|
size = drm_connector_get_gamma_size(output);
|
2018-10-03 08:36:33 +00:00
|
|
|
if (size == 0) {
|
2018-07-22 16:37:01 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-10-03 08:36:33 +00:00
|
|
|
uint16_t *gamma_table = malloc(3 * size * sizeof(uint16_t));
|
|
|
|
if (gamma_table == NULL) {
|
|
|
|
wlr_log(WLR_ERROR, "Failed to allocate gamma table");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
uint16_t *_r = gamma_table;
|
|
|
|
uint16_t *_g = gamma_table + size;
|
|
|
|
uint16_t *_b = gamma_table + 2 * size;
|
|
|
|
|
|
|
|
if (reset) {
|
|
|
|
fill_empty_gamma_table(size, _r, _g, _b);
|
|
|
|
} else {
|
|
|
|
memcpy(_r, r, size * sizeof(uint16_t));
|
|
|
|
memcpy(_g, g, size * sizeof(uint16_t));
|
|
|
|
memcpy(_b, b, size * sizeof(uint16_t));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ok = drm->iface->crtc_set_gamma(drm, conn->crtc, size, _r, _g, _b);
|
2018-07-22 16:37:01 +00:00
|
|
|
if (ok) {
|
|
|
|
wlr_output_update_needs_swap(output);
|
2018-10-03 08:53:35 +00:00
|
|
|
|
|
|
|
free(conn->crtc->gamma_table);
|
|
|
|
conn->crtc->gamma_table = gamma_table;
|
|
|
|
conn->crtc->gamma_table_size = size;
|
|
|
|
} else {
|
|
|
|
free(gamma_table);
|
2018-07-22 16:37:01 +00:00
|
|
|
}
|
|
|
|
return ok;
|
|
|
|
}
|
|
|
|
|
2018-05-21 17:50:51 +00:00
|
|
|
static bool drm_connector_export_dmabuf(struct wlr_output *output,
|
2018-05-31 11:33:27 +00:00
|
|
|
struct wlr_dmabuf_attributes *attribs) {
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-05-21 17:50:51 +00:00
|
|
|
|
|
|
|
if (!drm->session->active) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
|
|
|
if (!crtc) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
struct wlr_drm_plane *plane = crtc->primary;
|
|
|
|
struct wlr_drm_surface *surf = &plane->surf;
|
|
|
|
|
2018-05-22 22:07:15 +00:00
|
|
|
return export_drm_bo(surf->back, attribs);
|
2018-05-21 17:50:51 +00:00
|
|
|
}
|
|
|
|
|
2018-04-21 10:42:18 +00:00
|
|
|
static void drm_connector_start_renderer(struct wlr_drm_connector *conn) {
|
2017-09-30 10:31:08 +00:00
|
|
|
if (conn->state != WLR_DRM_CONN_CONNECTED) {
|
2017-05-14 00:48:47 +00:00
|
|
|
return;
|
2017-05-02 01:00:25 +00:00
|
|
|
}
|
2017-05-01 03:20:48 +00:00
|
|
|
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_DEBUG, "Starting renderer on output '%s'", conn->output.name);
|
2018-05-27 10:32:00 +00:00
|
|
|
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_backend *drm =
|
|
|
|
get_drm_backend_from_backend(conn->output.backend);
|
2017-09-30 10:31:08 +00:00
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
2018-01-21 20:37:23 +00:00
|
|
|
if (!crtc) {
|
|
|
|
return;
|
|
|
|
}
|
2017-08-05 05:27:59 +00:00
|
|
|
struct wlr_drm_plane *plane = crtc->primary;
|
2017-05-01 03:20:48 +00:00
|
|
|
|
2018-04-25 22:24:58 +00:00
|
|
|
struct gbm_bo *bo = get_drm_surface_front(
|
2017-10-01 06:22:47 +00:00
|
|
|
drm->parent ? &plane->mgpu_surf : &plane->surf);
|
2019-01-29 11:04:12 +00:00
|
|
|
uint32_t fb_id = get_fb_for_bo(bo, plane->drm_format);
|
2017-05-01 03:20:48 +00:00
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
struct wlr_drm_mode *mode = (struct wlr_drm_mode *)conn->output.current_mode;
|
|
|
|
if (drm->iface->crtc_pageflip(drm, conn, crtc, fb_id, &mode->drm_mode)) {
|
|
|
|
conn->pageflip_pending = true;
|
2018-02-02 21:27:18 +00:00
|
|
|
wlr_output_update_enabled(&conn->output, true);
|
2017-09-23 06:27:14 +00:00
|
|
|
} else {
|
2017-09-30 10:31:08 +00:00
|
|
|
wl_event_source_timer_update(conn->retry_pageflip,
|
2018-01-19 22:35:23 +00:00
|
|
|
1000000.0f / conn->output.current_mode->refresh);
|
2017-09-23 06:27:14 +00:00
|
|
|
}
|
2017-05-14 00:48:47 +00:00
|
|
|
}
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
static bool drm_connector_set_mode(struct wlr_output *output,
|
|
|
|
struct wlr_output_mode *mode);
|
|
|
|
|
|
|
|
static void realloc_crtcs(struct wlr_drm_backend *drm, bool *changed_outputs);
|
|
|
|
|
|
|
|
static void attempt_enable_needs_modeset(struct wlr_drm_backend *drm) {
|
|
|
|
// Try to modeset any output that has a desired mode and a CRTC (ie. was
|
|
|
|
// lacking a CRTC on last modeset)
|
|
|
|
struct wlr_drm_connector *conn;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
|
|
|
if (conn->state == WLR_DRM_CONN_NEEDS_MODESET &&
|
|
|
|
conn->crtc != NULL && conn->desired_mode != NULL &&
|
|
|
|
conn->desired_enabled) {
|
2019-01-19 09:14:01 +00:00
|
|
|
wlr_log(WLR_DEBUG, "Output %s has a desired mode and a CRTC, "
|
|
|
|
"attempting a modeset", conn->output.name);
|
2018-09-10 21:35:22 +00:00
|
|
|
drm_connector_set_mode(&conn->output, conn->desired_mode);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-09-14 16:18:07 +00:00
|
|
|
bool enable_drm_connector(struct wlr_output *output, bool enable) {
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-09-01 21:43:16 +00:00
|
|
|
if (conn->state != WLR_DRM_CONN_CONNECTED
|
|
|
|
&& conn->state != WLR_DRM_CONN_NEEDS_MODESET) {
|
2018-09-14 16:18:07 +00:00
|
|
|
return false;
|
2017-06-06 15:48:30 +00:00
|
|
|
}
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
conn->desired_enabled = enable;
|
|
|
|
|
|
|
|
if (enable && conn->crtc == NULL) {
|
|
|
|
// Maybe we can steal a CRTC from a disabled output
|
|
|
|
realloc_crtcs(drm, NULL);
|
|
|
|
}
|
|
|
|
|
2018-01-06 23:28:21 +00:00
|
|
|
bool ok = drm->iface->conn_enable(drm, conn, enable);
|
|
|
|
if (!ok) {
|
2018-09-14 16:18:07 +00:00
|
|
|
return false;
|
2018-01-06 23:28:21 +00:00
|
|
|
}
|
2017-06-06 15:48:30 +00:00
|
|
|
|
2017-08-09 08:43:01 +00:00
|
|
|
if (enable) {
|
2018-04-21 10:42:18 +00:00
|
|
|
drm_connector_start_renderer(conn);
|
2018-09-10 21:35:22 +00:00
|
|
|
} else {
|
|
|
|
realloc_crtcs(drm, NULL);
|
|
|
|
|
|
|
|
attempt_enable_needs_modeset(drm);
|
2017-07-29 10:14:29 +00:00
|
|
|
}
|
2018-01-04 11:46:15 +00:00
|
|
|
|
|
|
|
wlr_output_update_enabled(&conn->output, enable);
|
2018-09-14 16:18:07 +00:00
|
|
|
return true;
|
2017-07-29 10:14:29 +00:00
|
|
|
}
|
|
|
|
|
2018-12-04 17:56:29 +00:00
|
|
|
static ssize_t connector_index_from_crtc(struct wlr_drm_backend *drm,
|
|
|
|
struct wlr_drm_crtc *crtc) {
|
|
|
|
size_t i = 0;
|
|
|
|
struct wlr_drm_connector *conn;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
|
|
|
if (conn->crtc == crtc) {
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2017-10-22 10:15:02 +00:00
|
|
|
static void realloc_planes(struct wlr_drm_backend *drm, const uint32_t *crtc_in,
|
|
|
|
bool *changed_outputs) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_DEBUG, "Reallocating planes");
|
2018-05-27 10:32:00 +00:00
|
|
|
|
2017-08-05 05:27:59 +00:00
|
|
|
// overlay, primary, cursor
|
2018-05-27 10:32:00 +00:00
|
|
|
for (size_t type = 0; type < 3; ++type) {
|
2017-09-30 09:22:26 +00:00
|
|
|
if (drm->num_type_planes[type] == 0) {
|
2017-07-30 22:04:34 +00:00
|
|
|
continue;
|
2017-08-06 22:15:05 +00:00
|
|
|
}
|
2017-05-07 16:26:48 +00:00
|
|
|
|
2018-10-07 11:04:52 +00:00
|
|
|
uint32_t possible[drm->num_type_planes[type] + 1];
|
|
|
|
uint32_t crtc[drm->num_crtcs + 1];
|
|
|
|
uint32_t crtc_res[drm->num_crtcs + 1];
|
2017-05-07 16:26:48 +00:00
|
|
|
|
2017-09-30 09:22:26 +00:00
|
|
|
for (size_t i = 0; i < drm->num_type_planes[type]; ++i) {
|
|
|
|
possible[i] = drm->type_planes[type][i].possible_crtcs;
|
2017-08-06 22:15:05 +00:00
|
|
|
}
|
2017-05-07 16:26:48 +00:00
|
|
|
|
2017-09-30 09:22:26 +00:00
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
2017-08-06 22:15:05 +00:00
|
|
|
if (crtc_in[i] == UNMATCHED) {
|
2017-08-05 05:27:59 +00:00
|
|
|
crtc[i] = SKIP;
|
2017-09-30 09:22:26 +00:00
|
|
|
} else if (drm->crtcs[i].planes[type]) {
|
|
|
|
crtc[i] = drm->crtcs[i].planes[type]
|
|
|
|
- drm->type_planes[type];
|
2017-08-06 22:15:05 +00:00
|
|
|
} else {
|
2017-08-05 05:27:59 +00:00
|
|
|
crtc[i] = UNMATCHED;
|
2017-08-06 22:15:05 +00:00
|
|
|
}
|
2017-07-30 22:04:34 +00:00
|
|
|
}
|
|
|
|
|
2017-09-30 09:22:26 +00:00
|
|
|
match_obj(drm->num_type_planes[type], possible,
|
|
|
|
drm->num_crtcs, crtc, crtc_res);
|
2017-08-05 05:27:59 +00:00
|
|
|
|
2017-09-30 09:22:26 +00:00
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
2017-08-06 22:15:05 +00:00
|
|
|
if (crtc_res[i] == UNMATCHED || crtc_res[i] == SKIP) {
|
2017-08-05 05:27:59 +00:00
|
|
|
continue;
|
2017-08-06 22:15:05 +00:00
|
|
|
}
|
2017-07-29 10:14:29 +00:00
|
|
|
|
2017-09-30 09:22:26 +00:00
|
|
|
struct wlr_drm_crtc *c = &drm->crtcs[i];
|
2017-08-05 09:29:58 +00:00
|
|
|
struct wlr_drm_plane **old = &c->planes[type];
|
2017-09-30 09:22:26 +00:00
|
|
|
struct wlr_drm_plane *new = &drm->type_planes[type][crtc_res[i]];
|
2017-08-05 09:29:58 +00:00
|
|
|
|
|
|
|
if (*old != new) {
|
2018-09-04 13:09:07 +00:00
|
|
|
wlr_log(WLR_DEBUG,
|
|
|
|
"Assigning plane %d -> %d (type %zu) to CRTC %d",
|
2018-05-27 10:32:00 +00:00
|
|
|
*old ? (int)(*old)->id : -1,
|
|
|
|
new ? (int)new->id : -1,
|
2018-09-04 13:09:07 +00:00
|
|
|
type,
|
2018-05-27 10:32:00 +00:00
|
|
|
c->id);
|
|
|
|
|
2018-12-04 17:56:29 +00:00
|
|
|
ssize_t conn_idx = connector_index_from_crtc(drm, c);
|
|
|
|
if (conn_idx >= 0) {
|
|
|
|
changed_outputs[conn_idx] = true;
|
|
|
|
}
|
2017-09-30 07:52:58 +00:00
|
|
|
if (*old) {
|
2018-04-25 22:24:58 +00:00
|
|
|
finish_drm_surface(&(*old)->surf);
|
2017-09-30 07:52:58 +00:00
|
|
|
}
|
2018-04-25 22:24:58 +00:00
|
|
|
finish_drm_surface(&new->surf);
|
2017-08-05 09:29:58 +00:00
|
|
|
*old = new;
|
|
|
|
}
|
2017-05-07 16:26:48 +00:00
|
|
|
}
|
2017-08-05 05:27:59 +00:00
|
|
|
}
|
2017-07-30 22:04:34 +00:00
|
|
|
}
|
2017-05-07 16:26:48 +00:00
|
|
|
|
2018-04-21 10:42:18 +00:00
|
|
|
static void drm_connector_cleanup(struct wlr_drm_connector *conn);
|
|
|
|
|
|
|
|
static bool drm_connector_set_mode(struct wlr_output *output,
|
2017-09-30 10:31:08 +00:00
|
|
|
struct wlr_output_mode *mode) {
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-09-10 21:35:22 +00:00
|
|
|
if (conn->crtc == NULL) {
|
|
|
|
// Maybe we can steal a CRTC from a disabled output
|
|
|
|
realloc_crtcs(drm, NULL);
|
|
|
|
}
|
2018-09-04 13:09:07 +00:00
|
|
|
if (conn->crtc == NULL) {
|
|
|
|
wlr_log(WLR_ERROR, "Cannot modeset '%s': no CRTC for this connector",
|
|
|
|
conn->output.name);
|
|
|
|
// Save the desired mode for later, when we'll get a proper CRTC
|
|
|
|
conn->desired_mode = mode;
|
|
|
|
return false;
|
2017-07-30 22:04:34 +00:00
|
|
|
}
|
|
|
|
|
2018-09-04 13:09:07 +00:00
|
|
|
wlr_log(WLR_INFO, "Modesetting '%s' with '%ux%u@%u mHz'",
|
|
|
|
conn->output.name, mode->width, mode->height, mode->refresh);
|
2017-09-30 10:31:08 +00:00
|
|
|
|
2018-09-04 13:09:07 +00:00
|
|
|
if (!init_drm_plane_surfaces(conn->crtc->primary, drm,
|
2019-01-29 11:04:12 +00:00
|
|
|
mode->width, mode->height, drm->renderer.gbm_format)) {
|
2018-09-04 13:09:07 +00:00
|
|
|
wlr_log(WLR_ERROR, "Failed to initialize renderer for plane");
|
2018-09-01 23:03:20 +00:00
|
|
|
return false;
|
2018-01-21 20:37:23 +00:00
|
|
|
}
|
2017-05-07 16:26:48 +00:00
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
conn->state = WLR_DRM_CONN_CONNECTED;
|
2018-09-04 13:09:07 +00:00
|
|
|
conn->desired_mode = NULL;
|
2017-12-17 17:02:55 +00:00
|
|
|
wlr_output_update_mode(&conn->output, mode);
|
2018-09-04 13:09:07 +00:00
|
|
|
wlr_output_update_enabled(&conn->output, true);
|
2018-09-10 21:35:22 +00:00
|
|
|
conn->desired_enabled = true;
|
2018-09-04 13:09:07 +00:00
|
|
|
|
|
|
|
drm_connector_start_renderer(conn);
|
2017-05-07 16:26:48 +00:00
|
|
|
|
2018-04-17 23:15:25 +00:00
|
|
|
// When switching VTs, the mode is not updated but the buffers become
|
|
|
|
// invalid, so we need to manually damage the output here
|
|
|
|
wlr_output_damage_whole(&conn->output);
|
|
|
|
|
2017-05-07 16:26:48 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-06-28 10:35:55 +00:00
|
|
|
bool wlr_drm_connector_add_mode(struct wlr_output *output,
|
|
|
|
const drmModeModeInfo *modeinfo) {
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
2018-06-28 10:35:55 +00:00
|
|
|
|
|
|
|
if (modeinfo->type != DRM_MODE_TYPE_USERDEF) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-12-16 10:06:46 +00:00
|
|
|
struct wlr_output_mode *wlr_mode;
|
|
|
|
wl_list_for_each(wlr_mode, &conn->output.modes, link) {
|
|
|
|
struct wlr_drm_mode *mode = (struct wlr_drm_mode *)wlr_mode;
|
|
|
|
if (memcmp(&mode->drm_mode, modeinfo, sizeof(*modeinfo)) == 0) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-28 10:35:55 +00:00
|
|
|
struct wlr_drm_mode *mode = calloc(1, sizeof(*mode));
|
|
|
|
if (!mode) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
memcpy(&mode->drm_mode, modeinfo, sizeof(*modeinfo));
|
|
|
|
|
|
|
|
mode->wlr_mode.width = mode->drm_mode.hdisplay;
|
|
|
|
mode->wlr_mode.height = mode->drm_mode.vdisplay;
|
2018-12-16 10:06:46 +00:00
|
|
|
mode->wlr_mode.refresh = calculate_refresh_rate(modeinfo);
|
2018-06-28 10:35:55 +00:00
|
|
|
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, "Registered custom mode "
|
2018-06-28 10:35:55 +00:00
|
|
|
"%"PRId32"x%"PRId32"@%"PRId32,
|
|
|
|
mode->wlr_mode.width, mode->wlr_mode.height,
|
|
|
|
mode->wlr_mode.refresh);
|
|
|
|
wl_list_insert(&conn->output.modes, &mode->wlr_mode.link);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-04-21 10:42:18 +00:00
|
|
|
static void drm_connector_transform(struct wlr_output *output,
|
2017-06-06 15:48:30 +00:00
|
|
|
enum wl_output_transform transform) {
|
2017-08-13 14:51:50 +00:00
|
|
|
output->transform = transform;
|
2017-05-31 19:38:26 +00:00
|
|
|
}
|
|
|
|
|
2018-04-21 10:42:18 +00:00
|
|
|
static bool drm_connector_set_cursor(struct wlr_output *output,
|
2018-05-09 18:58:18 +00:00
|
|
|
struct wlr_texture *texture, int32_t scale,
|
2018-09-17 20:25:20 +00:00
|
|
|
enum wl_output_transform transform,
|
|
|
|
int32_t hotspot_x, int32_t hotspot_y, bool update_texture) {
|
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2017-09-30 10:31:08 +00:00
|
|
|
|
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
2018-01-21 19:57:24 +00:00
|
|
|
if (!crtc) {
|
|
|
|
return false;
|
|
|
|
}
|
2017-06-26 07:32:36 +00:00
|
|
|
|
2018-03-11 10:40:03 +00:00
|
|
|
struct wlr_drm_plane *plane = crtc->cursor;
|
2017-08-06 09:38:40 +00:00
|
|
|
if (!plane) {
|
2018-03-11 10:40:03 +00:00
|
|
|
// We don't have a real cursor plane, so we make a fake one
|
2017-08-06 09:38:40 +00:00
|
|
|
plane = calloc(1, sizeof(*plane));
|
|
|
|
if (!plane) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log_errno(WLR_ERROR, "Allocation failed");
|
2017-08-06 09:38:40 +00:00
|
|
|
return false;
|
2017-06-26 07:32:36 +00:00
|
|
|
}
|
2017-08-06 09:38:40 +00:00
|
|
|
crtc->cursor = plane;
|
|
|
|
}
|
2017-06-26 07:32:36 +00:00
|
|
|
|
2017-09-30 07:52:58 +00:00
|
|
|
if (!plane->surf.gbm) {
|
2017-08-06 09:38:40 +00:00
|
|
|
int ret;
|
|
|
|
uint64_t w, h;
|
2017-09-30 09:22:26 +00:00
|
|
|
ret = drmGetCap(drm->fd, DRM_CAP_CURSOR_WIDTH, &w);
|
2017-08-06 09:38:40 +00:00
|
|
|
w = ret ? 64 : w;
|
2017-09-30 09:22:26 +00:00
|
|
|
ret = drmGetCap(drm->fd, DRM_CAP_CURSOR_HEIGHT, &h);
|
2017-08-06 09:38:40 +00:00
|
|
|
h = ret ? 64 : h;
|
|
|
|
|
2018-08-04 03:03:34 +00:00
|
|
|
|
2019-02-05 22:39:30 +00:00
|
|
|
if (!drm->parent) {
|
|
|
|
if (!init_drm_surface(&plane->surf, &drm->renderer, w, h,
|
|
|
|
drm->renderer.gbm_format, GBM_BO_USE_LINEAR | GBM_BO_USE_SCANOUT)) {
|
|
|
|
wlr_log(WLR_ERROR, "Cannot allocate cursor resources");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (!init_drm_surface(&plane->surf, &drm->parent->renderer, w, h,
|
|
|
|
drm->parent->renderer.gbm_format, GBM_BO_USE_LINEAR)) {
|
|
|
|
wlr_log(WLR_ERROR, "Cannot allocate cursor resources");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!init_drm_surface(&plane->mgpu_surf, &drm->renderer, w, h,
|
|
|
|
drm->renderer.gbm_format, GBM_BO_USE_LINEAR | GBM_BO_USE_SCANOUT)) {
|
|
|
|
wlr_log(WLR_ERROR, "Cannot allocate cursor resources");
|
|
|
|
return false;
|
|
|
|
}
|
2017-06-26 07:32:36 +00:00
|
|
|
}
|
2017-06-16 19:38:34 +00:00
|
|
|
}
|
2017-06-26 07:32:36 +00:00
|
|
|
|
2018-05-16 13:14:57 +00:00
|
|
|
wlr_matrix_projection(plane->matrix, plane->surf.width,
|
|
|
|
plane->surf.height, output->transform);
|
|
|
|
|
2018-03-11 10:40:03 +00:00
|
|
|
struct wlr_box hotspot = { .x = hotspot_x, .y = hotspot_y };
|
2019-01-19 09:14:01 +00:00
|
|
|
wlr_box_transform(&hotspot, &hotspot,
|
2018-12-21 18:56:10 +00:00
|
|
|
wlr_output_transform_invert(output->transform),
|
|
|
|
plane->surf.width, plane->surf.height);
|
2017-10-29 17:45:53 +00:00
|
|
|
|
2018-03-11 14:06:06 +00:00
|
|
|
if (plane->cursor_hotspot_x != hotspot.x ||
|
|
|
|
plane->cursor_hotspot_y != hotspot.y) {
|
|
|
|
// Update cursor hotspot
|
|
|
|
conn->cursor_x -= hotspot.x - plane->cursor_hotspot_x;
|
|
|
|
conn->cursor_y -= hotspot.y - plane->cursor_hotspot_y;
|
|
|
|
plane->cursor_hotspot_x = hotspot.x;
|
|
|
|
plane->cursor_hotspot_y = hotspot.y;
|
|
|
|
|
|
|
|
if (!drm->iface->crtc_move_cursor(drm, conn->crtc, conn->cursor_x,
|
|
|
|
conn->cursor_y)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-03-11 10:40:03 +00:00
|
|
|
wlr_output_update_needs_swap(output);
|
2018-03-11 14:06:06 +00:00
|
|
|
}
|
|
|
|
|
2018-05-01 20:38:04 +00:00
|
|
|
if (!update_texture) {
|
2018-03-11 14:06:06 +00:00
|
|
|
// Don't update cursor image
|
2017-10-12 07:40:51 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-05-01 20:38:04 +00:00
|
|
|
plane->cursor_enabled = false;
|
|
|
|
if (texture != NULL) {
|
|
|
|
int width, height;
|
|
|
|
wlr_texture_get_size(texture, &width, &height);
|
2018-05-09 18:58:18 +00:00
|
|
|
width = width * output->scale / scale;
|
|
|
|
height = height * output->scale / scale;
|
2018-05-01 20:38:04 +00:00
|
|
|
|
|
|
|
if (width > (int)plane->surf.width || height > (int)plane->surf.height) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_ERROR, "Cursor too large (max %dx%d)",
|
2018-05-01 20:38:04 +00:00
|
|
|
(int)plane->surf.width, (int)plane->surf.height);
|
|
|
|
return false;
|
|
|
|
}
|
2017-08-07 09:07:42 +00:00
|
|
|
|
2018-04-25 22:24:58 +00:00
|
|
|
make_drm_surface_current(&plane->surf, NULL);
|
2017-06-26 05:34:15 +00:00
|
|
|
|
2018-03-20 22:10:42 +00:00
|
|
|
struct wlr_renderer *rend = plane->surf.renderer->wlr_rend;
|
2018-03-24 22:30:28 +00:00
|
|
|
|
2018-05-09 18:58:18 +00:00
|
|
|
struct wlr_box cursor_box = { .width = width, .height = height };
|
|
|
|
|
|
|
|
float matrix[9];
|
|
|
|
wlr_matrix_project_box(matrix, &cursor_box, transform, 0, plane->matrix);
|
|
|
|
|
2018-03-20 22:10:42 +00:00
|
|
|
wlr_renderer_begin(rend, plane->surf.width, plane->surf.height);
|
|
|
|
wlr_renderer_clear(rend, (float[]){ 0.0, 0.0, 0.0, 0.0 });
|
2018-05-09 18:58:18 +00:00
|
|
|
wlr_render_texture_with_matrix(rend, texture, matrix, 1.0);
|
2018-03-20 22:10:42 +00:00
|
|
|
wlr_renderer_end(rend);
|
2017-08-06 09:38:40 +00:00
|
|
|
|
2018-04-25 22:24:58 +00:00
|
|
|
swap_drm_surface_buffers(&plane->surf, NULL);
|
2018-03-11 10:40:03 +00:00
|
|
|
|
2018-05-01 20:38:04 +00:00
|
|
|
plane->cursor_enabled = true;
|
2018-03-11 10:40:03 +00:00
|
|
|
}
|
2017-08-07 09:07:42 +00:00
|
|
|
|
2018-02-02 20:01:59 +00:00
|
|
|
if (!drm->session->active) {
|
2018-03-11 10:40:03 +00:00
|
|
|
return true; // will be committed when session is resumed
|
2018-02-02 20:01:59 +00:00
|
|
|
}
|
|
|
|
|
Allow cursor render surface to be used as fb
In order for a surface to be used as a cursor plane framebuffer, it
appears that requiring the buffer to be linear is sufficient.
GBM_BO_USE_SCANOUT is added in case GBM_BO_USE_LINEAR isn't sufficient
on untested hardware.
Fixes #1323
Removed wlr_drm_plane.cursor_bo as it does not serve any purpose
anymore.
Relevant analysis (taken from the PR description):
While trying to implement a fix for #1323, I found that when exporting
the rendered surface into a DMA-BUF and reimporting it with
`GBM_BO_USE_CURSOR`, the resulting object does not appear to be valid.
After some digging (turning on drm-kms debugging and switching to legacy
mode), I managed to extract the following error: ```
[drm:__setplane_check.isra.1 [drm]] Invalid pixel format AR24
little-endian (0x34325241), modifier 0x100000000000001 ``` The format
itself refers to ARGB8888 which is the same format as
`renderer->gbm_format` used in master to create the cursor bo. However,
using `gbm_bo_create` with `GBM_BO_USE_CURSOR` results in a modifier of
0. A modifier of zero represents a linear buffer while the modifier of
the surface that is rendered to is `I915_FORMAT_MOD_X_TILED` (see
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/uapi/drm/drm_fourcc.h?h=v4.20.6#n263).
In order to fix this mismatch in modifier, I added the
`GBM_BO_USE_LINEAR` to the render surface and everything started to work
just fine. I wondered however, whether the export and import is really
necessary. I then decided to test if the back buffer of the render
surface works as well, and at least on my hardware (Intel HD 530 and
Intel UHD 620) it does. This is the patch in this PR and this requires
no exporting and importing.
I have to note that I cheated in order to import DMA_BUFs into a cursor
bo when doing the first tests, since on import the Intel drivers check
that the cursor is 64x64. This is strange since cursor sizes other than
64x64 have been around for quite some time now
(https://lists.freedesktop.org/archives/mesa-commit/2014-June/050268.html).
Removing this check made everything work fine. I later (while writing
this PR) found out that `__DRI_IMAGE_USE_CURSOR` (to which
`GBM_BO_USE_CURSOR` translates) has been deprecated in mesa
(https://gitlab.freedesktop.org/mesa/mesa/blob/master/include/GL/internal/dri_interface.h#L1296),
which makes me wonder what the usecase of `GBM_BO_USE_CURSOR` is. The
reason we never encountered this is that when specifying
`GBM_BO_USE_WRITE`, a dumb buffer is created trough DRM and the usage
flag never reaches the Intel driver directly. The relevant code is in
https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/gbm/backends/dri/gbm_dri.c#L1011-1089
. From this it seems that as long as the size, format and modifiers are
right, any surface can be used as a cursor.
2019-02-04 19:47:07 +00:00
|
|
|
struct gbm_bo *bo = plane->cursor_enabled ? plane->surf.back : NULL;
|
2019-02-18 18:42:48 +00:00
|
|
|
if (bo && drm->parent) {
|
|
|
|
bo = copy_drm_surface_mgpu(&plane->mgpu_surf, bo);
|
2019-02-05 22:39:30 +00:00
|
|
|
}
|
|
|
|
|
2019-02-15 14:59:09 +00:00
|
|
|
if (bo) {
|
|
|
|
// workaround for nouveau
|
|
|
|
// Buffers created with GBM_BO_USER_LINEAR are placed in NOUVEAU_GEM_DOMAIN_GART.
|
|
|
|
// When the bo is attached to the cursor plane it is moved to NOUVEAU_GEM_DOMAIN_VRAM.
|
|
|
|
// However, this does not wait for the render operations to complete, leaving an empty surface.
|
|
|
|
// see https://bugs.freedesktop.org/show_bug.cgi?id=109631
|
|
|
|
// The render operations can be waited for using:
|
|
|
|
glFinish();
|
|
|
|
}
|
2018-01-20 15:43:14 +00:00
|
|
|
bool ok = drm->iface->crtc_set_cursor(drm, crtc, bo);
|
|
|
|
if (ok) {
|
|
|
|
wlr_output_update_needs_swap(output);
|
|
|
|
}
|
|
|
|
return ok;
|
2017-06-16 19:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-04-21 10:42:18 +00:00
|
|
|
static bool drm_connector_move_cursor(struct wlr_output *output,
|
2017-06-16 19:38:34 +00:00
|
|
|
int x, int y) {
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-01-21 21:16:55 +00:00
|
|
|
if (!conn->crtc) {
|
2018-01-21 20:47:02 +00:00
|
|
|
return false;
|
|
|
|
}
|
2017-10-29 17:45:53 +00:00
|
|
|
struct wlr_drm_plane *plane = conn->crtc->cursor;
|
|
|
|
|
2018-01-26 21:11:09 +00:00
|
|
|
struct wlr_box box = { .x = x, .y = y };
|
|
|
|
|
|
|
|
int width, height;
|
2018-01-30 09:23:35 +00:00
|
|
|
wlr_output_transformed_resolution(output, &width, &height);
|
2017-08-20 20:02:39 +00:00
|
|
|
|
2017-11-01 13:25:41 +00:00
|
|
|
enum wl_output_transform transform =
|
|
|
|
wlr_output_transform_invert(output->transform);
|
2018-12-21 18:56:10 +00:00
|
|
|
wlr_box_transform(&box, &box, transform, width, height);
|
2017-08-20 20:02:39 +00:00
|
|
|
|
2017-12-05 21:23:01 +00:00
|
|
|
if (plane != NULL) {
|
2018-01-30 09:23:35 +00:00
|
|
|
box.x -= plane->cursor_hotspot_x;
|
|
|
|
box.y -= plane->cursor_hotspot_y;
|
2017-12-05 21:23:01 +00:00
|
|
|
}
|
2017-11-01 13:36:58 +00:00
|
|
|
|
2018-02-02 20:01:59 +00:00
|
|
|
conn->cursor_x = box.x;
|
|
|
|
conn->cursor_y = box.y;
|
|
|
|
|
|
|
|
if (!drm->session->active) {
|
2018-03-11 10:40:03 +00:00
|
|
|
return true; // will be committed when session is resumed
|
2018-02-02 20:01:59 +00:00
|
|
|
}
|
|
|
|
|
2018-01-30 09:23:35 +00:00
|
|
|
bool ok = drm->iface->crtc_move_cursor(drm, conn->crtc, box.x, box.y);
|
2018-01-20 15:43:14 +00:00
|
|
|
if (ok) {
|
|
|
|
wlr_output_update_needs_swap(output);
|
|
|
|
}
|
|
|
|
return ok;
|
2017-06-16 19:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-10-29 19:38:57 +00:00
|
|
|
static bool drm_connector_schedule_frame(struct wlr_output *output) {
|
2018-10-05 14:14:22 +00:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
|
|
|
if (!drm->session->active) {
|
2018-10-29 19:38:57 +00:00
|
|
|
return false;
|
2018-10-05 14:14:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// We need to figure out where we are in the vblank cycle
|
|
|
|
// TODO: try using drmWaitVBlank and fallback to pageflipping
|
|
|
|
|
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
|
|
|
if (!crtc) {
|
2018-10-29 19:38:57 +00:00
|
|
|
return false;
|
2018-10-05 14:14:22 +00:00
|
|
|
}
|
|
|
|
struct wlr_drm_plane *plane = crtc->primary;
|
|
|
|
struct gbm_bo *bo = plane->surf.back;
|
|
|
|
if (!bo) {
|
|
|
|
// We haven't swapped buffers yet -- can't do a pageflip
|
|
|
|
wlr_output_send_frame(output);
|
2018-10-29 19:38:57 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (drm->parent) {
|
|
|
|
bo = copy_drm_surface_mgpu(&plane->mgpu_surf, bo);
|
2018-10-05 14:14:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (conn->pageflip_pending) {
|
|
|
|
wlr_log(WLR_ERROR, "Skipping pageflip on output '%s'",
|
|
|
|
conn->output.name);
|
2018-10-29 19:38:57 +00:00
|
|
|
return true;
|
2018-10-05 14:14:22 +00:00
|
|
|
}
|
|
|
|
|
2019-01-29 11:04:12 +00:00
|
|
|
uint32_t fb_id = get_fb_for_bo(bo, plane->drm_format);
|
2018-10-05 14:14:22 +00:00
|
|
|
if (!drm->iface->crtc_pageflip(drm, conn, crtc, fb_id, NULL)) {
|
2018-10-29 19:38:57 +00:00
|
|
|
return false;
|
2018-10-05 14:14:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
conn->pageflip_pending = true;
|
|
|
|
wlr_output_update_enabled(output, true);
|
2018-10-29 19:38:57 +00:00
|
|
|
return true;
|
2018-10-05 14:14:22 +00:00
|
|
|
}
|
|
|
|
|
2018-04-21 10:42:18 +00:00
|
|
|
static void drm_connector_destroy(struct wlr_output *output) {
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
2018-04-21 10:42:18 +00:00
|
|
|
drm_connector_cleanup(conn);
|
2018-09-28 08:00:40 +00:00
|
|
|
drmModeFreeCrtc(conn->old_crtc);
|
2017-09-30 10:31:08 +00:00
|
|
|
wl_event_source_remove(conn->retry_pageflip);
|
2017-11-01 18:34:17 +00:00
|
|
|
wl_list_remove(&conn->link);
|
2017-09-30 10:31:08 +00:00
|
|
|
free(conn);
|
2017-05-07 16:26:48 +00:00
|
|
|
}
|
|
|
|
|
2018-04-21 10:42:18 +00:00
|
|
|
static const struct wlr_output_impl output_impl = {
|
2018-04-25 22:24:58 +00:00
|
|
|
.enable = enable_drm_connector,
|
2018-04-21 10:42:18 +00:00
|
|
|
.set_mode = drm_connector_set_mode,
|
|
|
|
.transform = drm_connector_transform,
|
|
|
|
.set_cursor = drm_connector_set_cursor,
|
|
|
|
.move_cursor = drm_connector_move_cursor,
|
|
|
|
.destroy = drm_connector_destroy,
|
|
|
|
.make_current = drm_connector_make_current,
|
|
|
|
.swap_buffers = drm_connector_swap_buffers,
|
2018-10-03 08:53:35 +00:00
|
|
|
.set_gamma = set_drm_connector_gamma,
|
2018-04-21 10:42:18 +00:00
|
|
|
.get_gamma_size = drm_connector_get_gamma_size,
|
2018-05-21 17:50:51 +00:00
|
|
|
.export_dmabuf = drm_connector_export_dmabuf,
|
2018-10-05 14:14:22 +00:00
|
|
|
.schedule_frame = drm_connector_schedule_frame,
|
2017-05-07 16:26:48 +00:00
|
|
|
};
|
|
|
|
|
2017-12-19 18:59:08 +00:00
|
|
|
bool wlr_output_is_drm(struct wlr_output *output) {
|
|
|
|
return output->impl == &output_impl;
|
|
|
|
}
|
|
|
|
|
2017-09-23 06:27:14 +00:00
|
|
|
static int retry_pageflip(void *data) {
|
2017-09-30 10:31:08 +00:00
|
|
|
struct wlr_drm_connector *conn = data;
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, "%s: Retrying pageflip", conn->output.name);
|
2018-04-21 10:42:18 +00:00
|
|
|
drm_connector_start_renderer(conn);
|
2017-09-23 06:44:39 +00:00
|
|
|
return 0;
|
2017-09-23 06:27:14 +00:00
|
|
|
}
|
|
|
|
|
2017-07-20 11:26:53 +00:00
|
|
|
static const int32_t subpixel_map[] = {
|
|
|
|
[DRM_MODE_SUBPIXEL_UNKNOWN] = WL_OUTPUT_SUBPIXEL_UNKNOWN,
|
|
|
|
[DRM_MODE_SUBPIXEL_HORIZONTAL_RGB] = WL_OUTPUT_SUBPIXEL_HORIZONTAL_RGB,
|
|
|
|
[DRM_MODE_SUBPIXEL_HORIZONTAL_BGR] = WL_OUTPUT_SUBPIXEL_HORIZONTAL_BGR,
|
|
|
|
[DRM_MODE_SUBPIXEL_VERTICAL_RGB] = WL_OUTPUT_SUBPIXEL_VERTICAL_RGB,
|
|
|
|
[DRM_MODE_SUBPIXEL_VERTICAL_BGR] = WL_OUTPUT_SUBPIXEL_VERTICAL_BGR,
|
|
|
|
[DRM_MODE_SUBPIXEL_NONE] = WL_OUTPUT_SUBPIXEL_NONE,
|
|
|
|
};
|
2017-05-13 08:37:15 +00:00
|
|
|
|
2018-09-04 13:09:07 +00:00
|
|
|
static void dealloc_crtc(struct wlr_drm_connector *conn) {
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_backend *drm =
|
|
|
|
get_drm_backend_from_backend(conn->output.backend);
|
2018-09-04 13:09:07 +00:00
|
|
|
if (conn->crtc == NULL) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-09-04 17:44:44 +00:00
|
|
|
wlr_log(WLR_DEBUG, "De-allocating CRTC %zu for output '%s'",
|
|
|
|
conn->crtc - drm->crtcs, conn->output.name);
|
|
|
|
|
2018-10-03 08:53:35 +00:00
|
|
|
set_drm_connector_gamma(&conn->output, 0, NULL, NULL, NULL);
|
|
|
|
|
2018-09-04 13:09:07 +00:00
|
|
|
for (size_t type = 0; type < 3; ++type) {
|
|
|
|
struct wlr_drm_plane *plane = conn->crtc->planes[type];
|
|
|
|
if (plane == NULL) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
finish_drm_surface(&plane->surf);
|
|
|
|
conn->crtc->planes[type] = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
drm->iface->conn_enable(drm, conn, false);
|
|
|
|
|
|
|
|
conn->crtc = NULL;
|
|
|
|
}
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
static void realloc_crtcs(struct wlr_drm_backend *drm, bool *changed_outputs) {
|
2018-09-04 13:09:07 +00:00
|
|
|
size_t num_outputs = wl_list_length(&drm->outputs);
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
if (changed_outputs == NULL) {
|
|
|
|
changed_outputs = calloc(num_outputs, sizeof(bool));
|
|
|
|
if (changed_outputs == NULL) {
|
|
|
|
wlr_log(WLR_ERROR, "Allocation failed");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-09-04 13:09:07 +00:00
|
|
|
wlr_log(WLR_DEBUG, "Reallocating CRTCs");
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
uint32_t crtc[drm->num_crtcs + 1];
|
2018-09-04 13:09:07 +00:00
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
|
|
|
crtc[i] = UNMATCHED;
|
|
|
|
}
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
struct wlr_drm_connector *connectors[num_outputs + 1];
|
|
|
|
|
|
|
|
uint32_t possible_crtc[num_outputs + 1];
|
2018-09-04 13:09:07 +00:00
|
|
|
memset(possible_crtc, 0, sizeof(possible_crtc));
|
|
|
|
|
|
|
|
wlr_log(WLR_DEBUG, "State before reallocation:");
|
|
|
|
ssize_t i = -1;
|
|
|
|
struct wlr_drm_connector *conn;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
|
|
|
i++;
|
2018-09-10 21:35:22 +00:00
|
|
|
connectors[i] = conn;
|
2018-09-04 13:09:07 +00:00
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
wlr_log(WLR_DEBUG, " '%s' crtc=%d state=%d desired_enabled=%d",
|
|
|
|
conn->output.name,
|
|
|
|
conn->crtc ? (int)(conn->crtc - drm->crtcs) : -1,
|
|
|
|
conn->state, conn->desired_enabled);
|
2018-09-04 13:09:07 +00:00
|
|
|
|
|
|
|
if (conn->crtc) {
|
|
|
|
crtc[conn->crtc - drm->crtcs] = i;
|
|
|
|
}
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
// Only search CRTCs for user-enabled outputs (that are already
|
|
|
|
// connected or in need of a modeset)
|
|
|
|
if ((conn->state == WLR_DRM_CONN_CONNECTED ||
|
|
|
|
conn->state == WLR_DRM_CONN_NEEDS_MODESET) &&
|
|
|
|
conn->desired_enabled) {
|
2018-09-04 13:09:07 +00:00
|
|
|
possible_crtc[i] = conn->possible_crtc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
uint32_t crtc_res[drm->num_crtcs + 1];
|
2018-09-04 13:09:07 +00:00
|
|
|
match_obj(wl_list_length(&drm->outputs), possible_crtc,
|
|
|
|
drm->num_crtcs, crtc, crtc_res);
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
bool matched[num_outputs + 1];
|
2018-09-04 13:09:07 +00:00
|
|
|
memset(matched, false, sizeof(matched));
|
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
|
|
|
if (crtc_res[i] != UNMATCHED) {
|
|
|
|
matched[crtc_res[i]] = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
|
|
|
// We don't want any of the current monitors to be deactivated
|
2018-09-10 21:35:22 +00:00
|
|
|
if (crtc[i] != UNMATCHED && !matched[crtc[i]] &&
|
|
|
|
connectors[crtc[i]]->desired_enabled) {
|
2018-09-04 13:09:07 +00:00
|
|
|
wlr_log(WLR_DEBUG, "Could not match a CRTC for connected output %d",
|
|
|
|
crtc[i]);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
2018-09-10 21:35:22 +00:00
|
|
|
if (crtc_res[i] == crtc[i]) {
|
2018-09-04 13:09:07 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
// De-allocate this CRTC on previous output
|
|
|
|
if (crtc[i] != UNMATCHED) {
|
|
|
|
changed_outputs[crtc[i]] = true;
|
|
|
|
dealloc_crtc(connectors[crtc[i]]);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Assign this CRTC to next output
|
|
|
|
if (crtc_res[i] != UNMATCHED) {
|
2018-09-04 13:09:07 +00:00
|
|
|
changed_outputs[crtc_res[i]] = true;
|
|
|
|
|
2018-09-10 16:44:31 +00:00
|
|
|
struct wlr_drm_connector *conn = connectors[crtc_res[i]];
|
|
|
|
dealloc_crtc(conn);
|
|
|
|
conn->crtc = &drm->crtcs[i];
|
2018-09-04 13:09:07 +00:00
|
|
|
|
|
|
|
wlr_log(WLR_DEBUG, "Assigning CRTC %zu to output %d -> %d '%s'",
|
2018-09-10 16:44:31 +00:00
|
|
|
i, crtc[i], crtc_res[i], conn->output.name);
|
2018-09-04 13:09:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
wlr_log(WLR_DEBUG, "State after reallocation:");
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
2018-09-10 21:35:22 +00:00
|
|
|
wlr_log(WLR_DEBUG, " '%s' crtc=%d state=%d desired_enabled=%d",
|
|
|
|
conn->output.name,
|
|
|
|
conn->crtc ? (int)(conn->crtc - drm->crtcs) : -1,
|
|
|
|
conn->state, conn->desired_enabled);
|
2018-09-04 13:09:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
realloc_planes(drm, crtc_res, changed_outputs);
|
|
|
|
|
|
|
|
// We need to reinitialize any plane that has changed
|
|
|
|
i = -1;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
|
|
|
i++;
|
|
|
|
struct wlr_output_mode *mode = conn->output.current_mode;
|
|
|
|
|
2019-01-19 09:14:01 +00:00
|
|
|
if (conn->state != WLR_DRM_CONN_CONNECTED || !changed_outputs[i]) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (conn->crtc == NULL) {
|
|
|
|
wlr_log(WLR_DEBUG, "Output has %s lost its CRTC",
|
|
|
|
conn->output.name);
|
|
|
|
conn->state = WLR_DRM_CONN_NEEDS_MODESET;
|
|
|
|
wlr_output_update_enabled(&conn->output, false);
|
|
|
|
conn->desired_mode = conn->output.current_mode;
|
|
|
|
wlr_output_update_mode(&conn->output, NULL);
|
2018-09-04 13:09:07 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!init_drm_plane_surfaces(conn->crtc->primary, drm,
|
2019-01-29 11:04:12 +00:00
|
|
|
mode->width, mode->height, drm->renderer.gbm_format)) {
|
2018-09-04 13:09:07 +00:00
|
|
|
wlr_log(WLR_ERROR, "Failed to initialize renderer for plane");
|
|
|
|
drm_connector_cleanup(conn);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
drm_connector_start_renderer(conn);
|
2018-09-04 21:10:37 +00:00
|
|
|
|
|
|
|
wlr_output_damage_whole(&conn->output);
|
2018-09-04 13:09:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-09 09:48:00 +00:00
|
|
|
static uint32_t get_possible_crtcs(int fd, drmModeRes *res,
|
|
|
|
drmModeConnector *conn, bool is_mst) {
|
|
|
|
uint32_t ret = 0;
|
2018-09-04 13:09:07 +00:00
|
|
|
|
2018-12-09 09:55:53 +00:00
|
|
|
for (int i = 0; i < conn->count_encoders; ++i) {
|
|
|
|
drmModeEncoder *enc = drmModeGetEncoder(fd, conn->encoders[i]);
|
2018-12-09 09:48:00 +00:00
|
|
|
if (!enc) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret |= enc->possible_crtcs;
|
|
|
|
|
|
|
|
drmModeFreeEncoder(enc);
|
2018-09-04 13:09:07 +00:00
|
|
|
}
|
|
|
|
|
2018-12-09 09:48:00 +00:00
|
|
|
// Sometimes DP MST connectors report no encoders, so we'll loop though
|
|
|
|
// all of the encoders of the MST type instead.
|
|
|
|
// TODO: See if there is a better solution.
|
|
|
|
|
|
|
|
if (!is_mst || ret) {
|
|
|
|
return ret;
|
2018-09-04 13:09:07 +00:00
|
|
|
}
|
|
|
|
|
2018-12-09 09:48:00 +00:00
|
|
|
for (int i = 0; i < res->count_encoders; ++i) {
|
2018-12-09 09:55:53 +00:00
|
|
|
drmModeEncoder *enc = drmModeGetEncoder(fd, res->encoders[i]);
|
2018-12-09 09:48:00 +00:00
|
|
|
if (!enc) {
|
|
|
|
continue;
|
|
|
|
}
|
2018-09-04 13:09:07 +00:00
|
|
|
|
2018-12-09 09:48:00 +00:00
|
|
|
if (enc->encoder_type == DRM_MODE_ENCODER_DPMST) {
|
|
|
|
ret |= enc->possible_crtcs;
|
|
|
|
}
|
|
|
|
|
|
|
|
drmModeFreeEncoder(enc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
2018-09-04 13:09:07 +00:00
|
|
|
}
|
|
|
|
|
2018-04-25 22:24:58 +00:00
|
|
|
void scan_drm_connectors(struct wlr_drm_backend *drm) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, "Scanning DRM connectors");
|
2017-05-04 09:58:11 +00:00
|
|
|
|
2017-09-30 09:22:26 +00:00
|
|
|
drmModeRes *res = drmModeGetResources(drm->fd);
|
2017-05-03 10:40:19 +00:00
|
|
|
if (!res) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log_errno(WLR_ERROR, "Failed to get DRM resources");
|
2017-05-03 10:40:19 +00:00
|
|
|
return;
|
2017-05-03 05:49:03 +00:00
|
|
|
}
|
2017-05-01 03:20:48 +00:00
|
|
|
|
2018-09-02 07:00:21 +00:00
|
|
|
size_t seen_len = wl_list_length(&drm->outputs);
|
2017-10-22 10:45:23 +00:00
|
|
|
// +1 so length can never be 0, which is undefined behaviour.
|
|
|
|
// Last element isn't used.
|
2018-09-02 07:00:21 +00:00
|
|
|
bool seen[seen_len + 1];
|
2018-09-01 23:03:20 +00:00
|
|
|
memset(seen, false, sizeof(seen));
|
|
|
|
size_t new_outputs_len = 0;
|
2018-09-02 07:00:21 +00:00
|
|
|
struct wlr_drm_connector *new_outputs[res->count_connectors + 1];
|
2017-09-09 10:41:23 +00:00
|
|
|
|
2017-05-03 10:40:19 +00:00
|
|
|
for (int i = 0; i < res->count_connectors; ++i) {
|
2017-09-30 10:31:08 +00:00
|
|
|
drmModeConnector *drm_conn = drmModeGetConnector(drm->fd,
|
2017-07-20 11:26:53 +00:00
|
|
|
res->connectors[i]);
|
2017-09-30 10:31:08 +00:00
|
|
|
if (!drm_conn) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log_errno(WLR_ERROR, "Failed to get DRM connector");
|
2017-05-03 10:40:19 +00:00
|
|
|
continue;
|
2017-05-01 03:20:48 +00:00
|
|
|
}
|
2017-10-22 21:38:30 +00:00
|
|
|
drmModeEncoder *curr_enc = drmModeGetEncoder(drm->fd,
|
|
|
|
drm_conn->encoder_id);
|
|
|
|
|
2018-12-09 09:05:03 +00:00
|
|
|
ssize_t index = -1;
|
2017-10-19 13:48:00 +00:00
|
|
|
struct wlr_drm_connector *c, *wlr_conn = NULL;
|
|
|
|
wl_list_for_each(c, &drm->outputs, link) {
|
|
|
|
index++;
|
|
|
|
if (c->id == drm_conn->connector_id) {
|
|
|
|
wlr_conn = c;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2017-10-22 21:38:30 +00:00
|
|
|
|
2017-10-19 13:48:00 +00:00
|
|
|
if (!wlr_conn) {
|
2017-09-30 10:31:08 +00:00
|
|
|
wlr_conn = calloc(1, sizeof(*wlr_conn));
|
|
|
|
if (!wlr_conn) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log_errno(WLR_ERROR, "Allocation failed");
|
2017-10-22 21:38:30 +00:00
|
|
|
drmModeFreeEncoder(curr_enc);
|
2017-09-30 10:31:08 +00:00
|
|
|
drmModeFreeConnector(drm_conn);
|
2017-07-20 11:26:53 +00:00
|
|
|
continue;
|
2017-05-07 16:26:48 +00:00
|
|
|
}
|
2018-01-04 11:46:15 +00:00
|
|
|
wlr_output_init(&wlr_conn->output, &drm->backend, &output_impl,
|
|
|
|
drm->display);
|
2017-05-03 10:40:19 +00:00
|
|
|
|
2017-09-30 09:22:26 +00:00
|
|
|
struct wl_event_loop *ev = wl_display_get_event_loop(drm->display);
|
2017-09-30 10:31:08 +00:00
|
|
|
wlr_conn->retry_pageflip = wl_event_loop_add_timer(ev, retry_pageflip,
|
|
|
|
wlr_conn);
|
2017-09-23 06:27:14 +00:00
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
wlr_conn->state = WLR_DRM_CONN_DISCONNECTED;
|
|
|
|
wlr_conn->id = drm_conn->connector_id;
|
2017-05-03 10:40:19 +00:00
|
|
|
|
2018-09-04 13:09:07 +00:00
|
|
|
snprintf(wlr_conn->output.name, sizeof(wlr_conn->output.name),
|
|
|
|
"%s-%"PRIu32, conn_get_name(drm_conn->connector_type),
|
|
|
|
drm_conn->connector_type_id);
|
|
|
|
|
2017-05-04 09:58:11 +00:00
|
|
|
if (curr_enc) {
|
2017-09-30 10:31:08 +00:00
|
|
|
wlr_conn->old_crtc = drmModeGetCrtc(drm->fd, curr_enc->crtc_id);
|
2017-05-04 09:58:11 +00:00
|
|
|
}
|
|
|
|
|
2018-12-09 09:05:03 +00:00
|
|
|
wl_list_insert(drm->outputs.prev, &wlr_conn->link);
|
2018-09-04 13:09:07 +00:00
|
|
|
wlr_log(WLR_INFO, "Found connector '%s'", wlr_conn->output.name);
|
2017-05-03 10:40:19 +00:00
|
|
|
} else {
|
2017-09-09 10:41:23 +00:00
|
|
|
seen[index] = true;
|
2017-05-01 03:20:48 +00:00
|
|
|
}
|
|
|
|
|
2017-10-22 21:38:30 +00:00
|
|
|
if (curr_enc) {
|
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
|
|
|
if (drm->crtcs[i].id == curr_enc->crtc_id) {
|
|
|
|
wlr_conn->crtc = &drm->crtcs[i];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
wlr_conn->crtc = NULL;
|
|
|
|
}
|
|
|
|
|
2018-10-04 12:11:37 +00:00
|
|
|
// This can only happen *after* hotplug, since we haven't read the
|
|
|
|
// connector properties yet
|
|
|
|
if (wlr_conn->props.link_status != 0) {
|
|
|
|
uint64_t link_status;
|
|
|
|
if (!get_drm_prop(drm->fd, wlr_conn->id,
|
|
|
|
wlr_conn->props.link_status, &link_status)) {
|
|
|
|
wlr_log(WLR_ERROR, "Failed to get link status for '%s'",
|
|
|
|
wlr_conn->output.name);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (link_status == DRM_MODE_LINK_STATUS_BAD) {
|
|
|
|
// We need to reload our list of modes and force a modeset
|
|
|
|
wlr_log(WLR_INFO, "Bad link for '%s'", wlr_conn->output.name);
|
|
|
|
drm_connector_cleanup(wlr_conn);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
if (wlr_conn->state == WLR_DRM_CONN_DISCONNECTED &&
|
|
|
|
drm_conn->connection == DRM_MODE_CONNECTED) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, "'%s' connected", wlr_conn->output.name);
|
|
|
|
wlr_log(WLR_DEBUG, "Current CRTC: %d",
|
2018-05-27 10:32:00 +00:00
|
|
|
wlr_conn->crtc ? (int)wlr_conn->crtc->id : -1);
|
2018-02-06 21:45:37 +00:00
|
|
|
|
|
|
|
wlr_conn->output.phys_width = drm_conn->mmWidth;
|
|
|
|
wlr_conn->output.phys_height = drm_conn->mmHeight;
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, "Physical size: %"PRId32"x%"PRId32,
|
2018-02-06 21:45:37 +00:00
|
|
|
wlr_conn->output.phys_width, wlr_conn->output.phys_height);
|
|
|
|
wlr_conn->output.subpixel = subpixel_map[drm_conn->subpixel];
|
|
|
|
|
2018-04-25 22:24:58 +00:00
|
|
|
get_drm_connector_props(drm->fd, wlr_conn->id, &wlr_conn->props);
|
2018-02-06 21:45:37 +00:00
|
|
|
|
|
|
|
size_t edid_len = 0;
|
2018-04-25 22:24:58 +00:00
|
|
|
uint8_t *edid = get_drm_prop_blob(drm->fd,
|
2018-02-06 21:45:37 +00:00
|
|
|
wlr_conn->id, wlr_conn->props.edid, &edid_len);
|
|
|
|
parse_edid(&wlr_conn->output, edid_len, edid);
|
|
|
|
free(edid);
|
|
|
|
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, "Detected modes:");
|
2017-05-03 10:40:19 +00:00
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
for (int i = 0; i < drm_conn->count_modes; ++i) {
|
|
|
|
struct wlr_drm_mode *mode = calloc(1, sizeof(*mode));
|
2017-08-16 07:23:21 +00:00
|
|
|
if (!mode) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log_errno(WLR_ERROR, "Allocation failed");
|
2017-08-16 07:23:21 +00:00
|
|
|
continue;
|
|
|
|
}
|
2018-11-21 19:23:48 +00:00
|
|
|
|
2018-11-22 17:52:52 +00:00
|
|
|
if (drm_conn->modes[i].flags & DRM_MODE_FLAG_INTERLACE) {
|
2018-11-21 19:23:48 +00:00
|
|
|
free(mode);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
mode->drm_mode = drm_conn->modes[i];
|
|
|
|
mode->wlr_mode.width = mode->drm_mode.hdisplay;
|
|
|
|
mode->wlr_mode.height = mode->drm_mode.vdisplay;
|
|
|
|
mode->wlr_mode.refresh = calculate_refresh_rate(&mode->drm_mode);
|
2017-05-03 10:40:19 +00:00
|
|
|
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, " %"PRId32"x%"PRId32"@%"PRId32,
|
2017-08-14 12:03:51 +00:00
|
|
|
mode->wlr_mode.width, mode->wlr_mode.height,
|
|
|
|
mode->wlr_mode.refresh);
|
2017-05-01 03:20:48 +00:00
|
|
|
|
2017-10-15 10:32:37 +00:00
|
|
|
wl_list_insert(&wlr_conn->output.modes, &mode->wlr_mode.link);
|
2017-05-03 05:49:03 +00:00
|
|
|
}
|
2017-05-01 03:20:48 +00:00
|
|
|
|
2018-12-09 09:48:00 +00:00
|
|
|
wlr_conn->possible_crtc = get_possible_crtcs(drm->fd, res, drm_conn,
|
|
|
|
wlr_conn->props.path != 0);
|
2018-09-04 13:09:07 +00:00
|
|
|
if (wlr_conn->possible_crtc == 0) {
|
|
|
|
wlr_log(WLR_ERROR, "No CRTC possible for connector '%s'",
|
|
|
|
wlr_conn->output.name);
|
|
|
|
}
|
|
|
|
|
2018-09-01 23:03:20 +00:00
|
|
|
wlr_output_update_enabled(&wlr_conn->output, wlr_conn->crtc != NULL);
|
2018-09-10 21:35:22 +00:00
|
|
|
wlr_conn->desired_enabled = true;
|
2017-10-22 20:21:23 +00:00
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
wlr_conn->state = WLR_DRM_CONN_NEEDS_MODESET;
|
2018-09-01 23:03:20 +00:00
|
|
|
new_outputs[new_outputs_len++] = wlr_conn;
|
2018-12-09 09:05:03 +00:00
|
|
|
} else if ((wlr_conn->state == WLR_DRM_CONN_CONNECTED ||
|
|
|
|
wlr_conn->state == WLR_DRM_CONN_NEEDS_MODESET) &&
|
2017-09-30 10:31:08 +00:00
|
|
|
drm_conn->connection != DRM_MODE_CONNECTED) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, "'%s' disconnected", wlr_conn->output.name);
|
2017-10-22 20:21:23 +00:00
|
|
|
|
2018-04-21 10:42:18 +00:00
|
|
|
drm_connector_cleanup(wlr_conn);
|
2017-05-01 03:20:48 +00:00
|
|
|
}
|
|
|
|
|
2017-10-22 21:38:30 +00:00
|
|
|
drmModeFreeEncoder(curr_enc);
|
2017-09-30 10:31:08 +00:00
|
|
|
drmModeFreeConnector(drm_conn);
|
2017-05-01 03:20:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
drmModeFreeResources(res);
|
2017-09-09 10:41:23 +00:00
|
|
|
|
2018-12-09 09:05:03 +00:00
|
|
|
// Iterate in reverse order because we'll remove items from the list and
|
|
|
|
// still want indices to remain correct.
|
2017-10-19 13:48:00 +00:00
|
|
|
struct wlr_drm_connector *conn, *tmp_conn;
|
2017-10-22 10:45:23 +00:00
|
|
|
size_t index = wl_list_length(&drm->outputs);
|
2018-12-09 09:05:03 +00:00
|
|
|
wl_list_for_each_reverse_safe(conn, tmp_conn, &drm->outputs, link) {
|
2017-10-22 10:45:23 +00:00
|
|
|
index--;
|
2018-09-02 07:00:21 +00:00
|
|
|
if (index >= seen_len || seen[index]) {
|
2017-09-09 10:41:23 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, "'%s' disappeared", conn->output.name);
|
2018-04-21 10:42:18 +00:00
|
|
|
drm_connector_cleanup(conn);
|
2017-09-09 10:41:23 +00:00
|
|
|
|
2018-09-28 08:00:40 +00:00
|
|
|
if (conn->pageflip_pending) {
|
|
|
|
conn->state = WLR_DRM_CONN_DISAPPEARED;
|
|
|
|
} else {
|
|
|
|
wlr_output_destroy(&conn->output);
|
|
|
|
}
|
2017-09-09 10:41:23 +00:00
|
|
|
}
|
2018-09-01 23:03:20 +00:00
|
|
|
|
2018-10-07 11:04:52 +00:00
|
|
|
bool changed_outputs[wl_list_length(&drm->outputs) + 1];
|
2018-09-04 13:09:07 +00:00
|
|
|
memset(changed_outputs, false, sizeof(changed_outputs));
|
|
|
|
for (size_t i = 0; i < new_outputs_len; ++i) {
|
|
|
|
struct wlr_drm_connector *conn = new_outputs[i];
|
|
|
|
|
|
|
|
ssize_t pos = -1;
|
|
|
|
struct wlr_drm_connector *c;
|
|
|
|
wl_list_for_each(c, &drm->outputs, link) {
|
|
|
|
++pos;
|
|
|
|
if (c == conn) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
assert(pos >= 0);
|
|
|
|
|
|
|
|
changed_outputs[pos] = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
realloc_crtcs(drm, changed_outputs);
|
|
|
|
|
2018-09-01 23:03:20 +00:00
|
|
|
for (size_t i = 0; i < new_outputs_len; ++i) {
|
|
|
|
struct wlr_drm_connector *conn = new_outputs[i];
|
|
|
|
|
|
|
|
wlr_log(WLR_INFO, "Requesting modeset for '%s'",
|
|
|
|
conn->output.name);
|
|
|
|
wlr_signal_emit_safe(&drm->backend.events.new_output,
|
|
|
|
&conn->output);
|
|
|
|
}
|
2018-09-04 13:09:07 +00:00
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
attempt_enable_needs_modeset(drm);
|
2017-05-01 03:20:48 +00:00
|
|
|
}
|
|
|
|
|
2018-10-02 10:11:09 +00:00
|
|
|
static int mhz_to_nsec(int mhz) {
|
|
|
|
return 1000000000000LL / mhz;
|
|
|
|
}
|
|
|
|
|
2017-05-07 14:00:23 +00:00
|
|
|
static void page_flip_handler(int fd, unsigned seq,
|
2018-09-29 20:38:13 +00:00
|
|
|
unsigned tv_sec, unsigned tv_usec, void *data) {
|
|
|
|
struct wlr_drm_connector *conn = data;
|
2018-09-17 20:25:20 +00:00
|
|
|
struct wlr_drm_backend *drm =
|
|
|
|
get_drm_backend_from_backend(conn->output.backend);
|
2017-05-03 10:40:19 +00:00
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
conn->pageflip_pending = false;
|
2018-09-28 08:00:40 +00:00
|
|
|
|
|
|
|
if (conn->state == WLR_DRM_CONN_DISAPPEARED) {
|
|
|
|
wlr_output_destroy(&conn->output);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
if (conn->state != WLR_DRM_CONN_CONNECTED || conn->crtc == NULL) {
|
2017-08-10 23:12:41 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-04-25 22:24:58 +00:00
|
|
|
post_drm_surface(&conn->crtc->primary->surf);
|
2017-10-01 06:22:47 +00:00
|
|
|
if (drm->parent) {
|
2018-04-25 22:24:58 +00:00
|
|
|
post_drm_surface(&conn->crtc->primary->mgpu_surf);
|
2017-06-09 05:15:55 +00:00
|
|
|
}
|
|
|
|
|
2018-09-29 20:38:13 +00:00
|
|
|
struct timespec present_time = {
|
|
|
|
.tv_sec = tv_sec,
|
|
|
|
.tv_nsec = tv_usec * 1000,
|
|
|
|
};
|
2018-10-02 10:11:09 +00:00
|
|
|
struct wlr_output_event_present present_event = {
|
|
|
|
.when = &present_time,
|
|
|
|
.seq = seq,
|
|
|
|
.refresh = mhz_to_nsec(conn->output.refresh),
|
|
|
|
.flags = WLR_OUTPUT_PRESENT_VSYNC | WLR_OUTPUT_PRESENT_HW_CLOCK |
|
|
|
|
WLR_OUTPUT_PRESENT_HW_COMPLETION,
|
|
|
|
};
|
|
|
|
wlr_output_send_present(&conn->output, &present_event);
|
2018-09-29 20:38:13 +00:00
|
|
|
|
2017-09-30 09:22:26 +00:00
|
|
|
if (drm->session->active) {
|
2018-01-26 21:39:23 +00:00
|
|
|
wlr_output_send_frame(&conn->output);
|
2017-05-03 05:49:03 +00:00
|
|
|
}
|
2017-05-03 10:40:19 +00:00
|
|
|
}
|
2017-05-01 03:20:48 +00:00
|
|
|
|
2018-04-25 22:24:58 +00:00
|
|
|
int handle_drm_event(int fd, uint32_t mask, void *data) {
|
2017-05-03 10:40:19 +00:00
|
|
|
drmEventContext event = {
|
2018-10-09 10:29:34 +00:00
|
|
|
.version = 2,
|
2017-05-03 10:40:19 +00:00
|
|
|
.page_flip_handler = page_flip_handler,
|
|
|
|
};
|
2017-05-01 05:49:18 +00:00
|
|
|
|
2017-05-03 10:40:19 +00:00
|
|
|
drmHandleEvent(fd, &event);
|
|
|
|
return 1;
|
|
|
|
}
|
2017-05-02 01:00:25 +00:00
|
|
|
|
2018-04-25 22:24:58 +00:00
|
|
|
void restore_drm_outputs(struct wlr_drm_backend *drm) {
|
2018-06-30 00:59:44 +00:00
|
|
|
uint64_t to_close = (1L << wl_list_length(&drm->outputs)) - 1;
|
2017-09-23 04:32:25 +00:00
|
|
|
|
2017-10-19 13:48:00 +00:00
|
|
|
struct wlr_drm_connector *conn;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
2017-09-30 10:31:08 +00:00
|
|
|
if (conn->state == WLR_DRM_CONN_CONNECTED) {
|
|
|
|
conn->state = WLR_DRM_CONN_CLEANUP;
|
2017-09-23 04:32:25 +00:00
|
|
|
}
|
2017-05-04 09:58:11 +00:00
|
|
|
}
|
|
|
|
|
2017-09-23 04:32:25 +00:00
|
|
|
time_t timeout = time(NULL) + 5;
|
|
|
|
|
|
|
|
while (to_close && time(NULL) < timeout) {
|
2018-04-25 22:24:58 +00:00
|
|
|
handle_drm_event(drm->fd, 0, NULL);
|
2017-10-19 13:48:00 +00:00
|
|
|
size_t i = 0;
|
|
|
|
struct wlr_drm_connector *conn;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
2017-09-30 10:31:08 +00:00
|
|
|
if (conn->state != WLR_DRM_CONN_CLEANUP || !conn->pageflip_pending) {
|
2017-09-23 04:32:25 +00:00
|
|
|
to_close &= ~(1 << i);
|
|
|
|
}
|
2017-10-19 13:48:00 +00:00
|
|
|
i++;
|
2017-09-23 04:32:25 +00:00
|
|
|
}
|
2017-05-03 05:49:03 +00:00
|
|
|
}
|
2017-05-02 01:00:25 +00:00
|
|
|
|
2017-09-23 04:32:25 +00:00
|
|
|
if (to_close) {
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_ERROR, "Timed out stopping output renderers");
|
2017-09-23 04:32:25 +00:00
|
|
|
}
|
|
|
|
|
2017-10-19 13:48:00 +00:00
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
2017-09-30 10:31:08 +00:00
|
|
|
drmModeCrtc *crtc = conn->old_crtc;
|
2017-09-23 04:32:25 +00:00
|
|
|
if (!crtc) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
drmModeSetCrtc(drm->fd, crtc->crtc_id, crtc->buffer_id, crtc->x, crtc->y,
|
2017-09-30 10:31:08 +00:00
|
|
|
&conn->id, 1, &crtc->mode);
|
2017-09-23 04:32:25 +00:00
|
|
|
}
|
2017-05-01 03:20:48 +00:00
|
|
|
}
|
|
|
|
|
2018-04-21 10:42:18 +00:00
|
|
|
static void drm_connector_cleanup(struct wlr_drm_connector *conn) {
|
2017-09-30 10:31:08 +00:00
|
|
|
if (!conn) {
|
2017-05-03 10:40:19 +00:00
|
|
|
return;
|
|
|
|
}
|
2017-05-01 03:20:48 +00:00
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
switch (conn->state) {
|
|
|
|
case WLR_DRM_CONN_CONNECTED:
|
|
|
|
case WLR_DRM_CONN_CLEANUP:;
|
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
2018-09-10 21:35:22 +00:00
|
|
|
if (crtc != NULL) {
|
|
|
|
for (int i = 0; i < 3; ++i) {
|
|
|
|
if (!crtc->planes[i]) {
|
|
|
|
continue;
|
|
|
|
}
|
2017-10-01 09:44:24 +00:00
|
|
|
|
2018-09-10 21:35:22 +00:00
|
|
|
finish_drm_surface(&crtc->planes[i]->surf);
|
|
|
|
finish_drm_surface(&crtc->planes[i]->mgpu_surf);
|
|
|
|
if (crtc->planes[i]->id == 0) {
|
|
|
|
free(crtc->planes[i]);
|
|
|
|
crtc->planes[i] = NULL;
|
|
|
|
}
|
2017-08-06 09:38:40 +00:00
|
|
|
}
|
|
|
|
}
|
2017-08-05 09:29:58 +00:00
|
|
|
|
2018-05-27 10:32:00 +00:00
|
|
|
conn->output.current_mode = NULL;
|
2018-09-04 13:09:07 +00:00
|
|
|
conn->desired_mode = NULL;
|
2018-05-27 10:32:00 +00:00
|
|
|
struct wlr_drm_mode *mode, *tmp;
|
2018-02-06 21:45:37 +00:00
|
|
|
wl_list_for_each_safe(mode, tmp, &conn->output.modes, wlr_mode.link) {
|
|
|
|
wl_list_remove(&mode->wlr_mode.link);
|
|
|
|
free(mode);
|
|
|
|
}
|
|
|
|
|
2018-09-04 13:09:07 +00:00
|
|
|
conn->output.enabled = false;
|
|
|
|
conn->output.width = conn->output.height = conn->output.refresh = 0;
|
|
|
|
|
2018-02-06 21:45:37 +00:00
|
|
|
memset(&conn->output.make, 0, sizeof(conn->output.make));
|
|
|
|
memset(&conn->output.model, 0, sizeof(conn->output.model));
|
|
|
|
memset(&conn->output.serial, 0, sizeof(conn->output.serial));
|
|
|
|
|
2018-10-09 08:25:38 +00:00
|
|
|
if (conn->output.idle_frame != NULL) {
|
|
|
|
wl_event_source_remove(conn->output.idle_frame);
|
|
|
|
conn->output.idle_frame = NULL;
|
|
|
|
}
|
|
|
|
conn->output.needs_swap = false;
|
|
|
|
conn->output.frame_pending = false;
|
|
|
|
|
2017-05-03 10:40:19 +00:00
|
|
|
/* Fallthrough */
|
2017-09-30 10:31:08 +00:00
|
|
|
case WLR_DRM_CONN_NEEDS_MODESET:
|
2018-07-09 21:49:54 +00:00
|
|
|
wlr_log(WLR_INFO, "Emitting destruction signal for '%s'",
|
2018-02-12 09:36:43 +00:00
|
|
|
conn->output.name);
|
2018-09-04 13:09:07 +00:00
|
|
|
dealloc_crtc(conn);
|
|
|
|
conn->possible_crtc = 0;
|
|
|
|
conn->desired_mode = NULL;
|
2018-02-12 09:36:43 +00:00
|
|
|
wlr_signal_emit_safe(&conn->output.events.destroy, &conn->output);
|
2017-05-03 10:40:19 +00:00
|
|
|
break;
|
2017-09-30 10:31:08 +00:00
|
|
|
case WLR_DRM_CONN_DISCONNECTED:
|
2017-05-03 10:40:19 +00:00
|
|
|
break;
|
2018-09-28 08:00:40 +00:00
|
|
|
case WLR_DRM_CONN_DISAPPEARED:
|
|
|
|
return; // don't change state
|
2017-05-03 10:40:19 +00:00
|
|
|
}
|
2017-09-23 23:06:00 +00:00
|
|
|
|
2017-09-30 10:31:08 +00:00
|
|
|
conn->state = WLR_DRM_CONN_DISCONNECTED;
|
2017-05-13 08:37:15 +00:00
|
|
|
}
|