backend/drm: introduce drm_fb_create
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5b1b43c68c
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cd64610c66
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@ -363,38 +363,32 @@ static struct gbm_bo *get_bo_for_dmabuf(struct gbm_device *gbm,
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}
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}
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bool drm_fb_import(struct wlr_drm_fb **fb_ptr, struct wlr_drm_backend *drm,
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struct wlr_buffer *buf, struct wlr_drm_surface *mgpu,
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struct wlr_drm_format_set *set) {
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static struct wlr_drm_fb *drm_fb_create(struct wlr_drm_backend *drm,
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struct wlr_buffer *buf, struct wlr_buffer *mgpu_buf,
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const struct wlr_drm_format_set *formats) {
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struct wlr_drm_fb *fb = calloc(1, sizeof(*fb));
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if (!fb) {
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return false;
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return NULL;
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}
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fb->wlr_buf = wlr_buffer_lock(buf);
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if (drm->parent && mgpu) {
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// Perform a copy across GPUs
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fb->mgpu_wlr_buf = drm_surface_blit(mgpu, buf);
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if (!fb->mgpu_wlr_buf) {
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wlr_log(WLR_ERROR, "Failed to blit buffer across GPUs");
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goto error_mgpu_wlr_buf;
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}
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buf = fb->mgpu_wlr_buf;
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if (mgpu_buf) {
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fb->mgpu_wlr_buf = wlr_buffer_lock(mgpu_buf);
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}
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struct wlr_buffer *local_buf = mgpu_buf ? mgpu_buf : buf;
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struct wlr_dmabuf_attributes attribs;
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if (!wlr_buffer_get_dmabuf(buf, &attribs)) {
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if (!wlr_buffer_get_dmabuf(local_buf, &attribs)) {
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wlr_log(WLR_ERROR, "Failed to get DMA-BUF from buffer");
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goto error_get_dmabuf;
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}
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if (set && !wlr_drm_format_set_has(set, attribs.format, attribs.modifier)) {
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if (formats && !wlr_drm_format_set_has(formats, attribs.format,
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attribs.modifier)) {
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// The format isn't supported by the plane. Try stripping the alpha
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// channel, if any.
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uint32_t format = strip_alpha_channel(attribs.format);
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if (wlr_drm_format_set_has(set, format, attribs.modifier)) {
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if (wlr_drm_format_set_has(formats, format, attribs.modifier)) {
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attribs.format = format;
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} else {
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wlr_log(WLR_ERROR, "Buffer format 0x%"PRIX32" cannot be scanned out",
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@ -415,18 +409,38 @@ bool drm_fb_import(struct wlr_drm_fb **fb_ptr, struct wlr_drm_backend *drm,
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goto error_get_fb_for_bo;
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}
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drm_fb_move(fb_ptr, &fb);
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return true;
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return fb;
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error_get_fb_for_bo:
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gbm_bo_destroy(fb->bo);
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error_get_dmabuf:
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wlr_buffer_unlock(fb->mgpu_wlr_buf);
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error_mgpu_wlr_buf:
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wlr_buffer_unlock(fb->wlr_buf);
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free(fb);
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return false;
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return NULL;
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}
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bool drm_fb_import(struct wlr_drm_fb **fb_ptr, struct wlr_drm_backend *drm,
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struct wlr_buffer *buf, struct wlr_drm_surface *mgpu,
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const struct wlr_drm_format_set *formats) {
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struct wlr_buffer *mgpu_buf = NULL;
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if (drm->parent && mgpu) {
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// Perform a copy across GPUs
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mgpu_buf = drm_surface_blit(mgpu, buf);
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if (!mgpu_buf) {
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wlr_log(WLR_ERROR, "Failed to blit buffer across GPUs");
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return false;
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}
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}
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struct wlr_drm_fb *fb = drm_fb_create(drm, buf, mgpu_buf, formats);
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wlr_buffer_unlock(mgpu_buf);
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if (!fb) {
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return false;
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}
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drm_fb_move(fb_ptr, &fb);
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return true;
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}
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void drm_fb_move(struct wlr_drm_fb **new, struct wlr_drm_fb **old) {
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@ -49,7 +49,7 @@ bool drm_fb_lock_surface(struct wlr_drm_fb **fb, struct wlr_drm_backend *drm,
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struct wlr_drm_surface *surf, struct wlr_drm_surface *mgpu);
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bool drm_fb_import(struct wlr_drm_fb **fb, struct wlr_drm_backend *drm,
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struct wlr_buffer *buf, struct wlr_drm_surface *mgpu,
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struct wlr_drm_format_set *set);
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const struct wlr_drm_format_set *formats);
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void drm_fb_clear(struct wlr_drm_fb **fb);
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void drm_fb_move(struct wlr_drm_fb **new, struct wlr_drm_fb **old);
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